Principal Engineer — Synthesis Team

Job Title

Principal Engineer — Synthesis Team

Role Summary

Lead architecture, design, and development of the FPGA synthesis toolchain for Lattice product families. Own technical direction and quality-of-results (QoR) for synthesis across area, timing (Fmax), runtime, and memory.

Work within the synthesis team and across functions (tooling, silicon, product) to deliver scalable, maintainable synthesis solutions that support the product roadmap.

Experience Level

Senior — the role expects 10+ years of experience in EDA software development, with domain expertise in logic synthesis or place-and-route.

Responsibilities

Primary responsibilities include technical leadership, algorithm design, and delivery of synthesis features and QoR improvements.

• Provide technical leadership for design, implementation, and optimization of synthesis engines across multiple product families.
• Define architecture, algorithms, and long-term technical direction in collaboration with synthesis developers and cross-functional partners.
• Drive QoR improvements targeting Fmax, area efficiency, compile time, and memory utilization.
• Lead development and enablement of new synthesis features aligned with product priorities.
• Maintain, modernize, and scale the synthesis codebase for robustness and long-term maintainability.
• Act as technical escalation point for complex synthesis and customer-reported issues.
• Influence engineering best practices, code quality, and design standards within the team.
• Mentor and guide junior and mid-level engineers through design reviews and technical coaching.

Requirements

Required qualifications are listed first; preferred or nice-to-have skills follow.

Must-have:

• 10+ years in EDA software development focused on logic synthesis or place-and-route.
• Expert-level proficiency in C++ with experience designing and optimizing large, performance-critical systems.
• Deep knowledge of synthesis algorithms, including technology mapping, retiming, logic optimization, and timing-driven optimization.
• Strong understanding of FPGA architectures (LUTs, DSPs, BRAMs, carry chains) and how architecture drives synthesis strategy.
• Experience with QoR benchmarking methodologies and data-driven optimization workflows.
• Proven ability to lead technical initiatives and influence cross-functional teams.
• Hands-on experience using generative AI tools to improve developer productivity (e.g., debugging, code review, algorithm exploration).

Nice-to-have:

• Familiarity with the Lattice synthesis toolchain (Radiant, Propel, ACE).
• Python scripting experience for automation, regression testing, or QoR analysis.

Education Requirements

Preferred: M.S. or Ph.D. in Computer Science, Electrical Engineering, or a related technical field (listed as preferred in the source). No mandatory minimum degree was specified.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.