Principal Engineer, SoC Design

Job Title

Principal Engineer, SoC Design

Role Summary

Technical leadership role owning SoC implementation from micro-architecture through tapeout and post-silicon validation. You will coordinate front-end design, verification, physical design, DFT/DFX, packaging and manufacturing to deliver high-performance silicon.

Work cross-functionally with architecture, verification, physical design and manufacturing teams to ensure implementation decisions are feasible and on schedule.

Experience Level

Senior-level - requires 15+ years of hands-on SoC front-end design and implementation experience.

Responsibilities

Deliver and oversee SoC implementation and team execution.

• Own chip implementation end-to-end: front-end design, verification integration, physical design coordination, DFT/DFX, packaging and manufacturing interaction.
• Drive design-to-spec execution: lint, CDC, LEC, synthesis, SDC constraints and full design convergence.
• Evaluate and integrate IP, balancing performance, power, area, cost and schedule.
• Coordinate implementation decisions with architecture, verification, DFX, physical design, packaging and manufacturing to ensure feasibility and schedule compliance.
• Establish and enforce implementation best practices, review standards and sign-off infrastructure.
• Lead and mentor design and implementation engineers; plan resources and mitigate risks.
• Oversee tapeout and post-silicon validation activities.

Requirements

Must-have technical skills and leadership experience.

• 15+ years of hands-on SoC front-end design and implementation with multiple successful high-performance tapeouts.
• Deep expertise in on-chip interconnect, power management and IO subsystem design.
• Strong knowledge of physical design: floorplanning, timing convergence and power integrity.
• Hands-on experience with lint, CDC/RDC, LEC, synthesis, SDC development and formal verification.
• Solid knowledge of DFT/DFX methods: scan insertion, ATPG, MBIST and JTAG.
• Proficient with industry-standard EDA tools across the implementation stack.
• Strong scripting skills (Python, Perl, Tcl, Shell).
• Proven leadership and communication skills with ability to drive complex programs in fast-paced environments.

Nice-to-have:

• Experience with 3D integration techniques.
• Background in high-bandwidth memory subsystem design and familiarity with AI workload memory demands.
• Experience with emulation and prototyping platforms.
• Prior startup experience delivering silicon with lean teams and aggressive schedules.

Education Requirements

B.Tech, M.Tech or MS in Electrical Engineering, ECE, Computer Engineering or a related field.

About the Company

Company: Keplercompute

Headquarters: San Jose, California, United States

Kepler is a semiconductor startup developing a new class of AI memory and logic using advanced materials and 3D architectures to build UHBM-based 3D-memory AI accelerator platforms. The team includes experienced semiconductor veterans and partners with foundries and customers to move lab technologies toward production.