Principal Engineer, SoC Architecture

Job Title

Principal Engineer, SoC Architecture

Role Summary

Lead the SoC architecture for Kepler's AI-focused silicon products. The role covers platform and micro-architecture, memory architecture, high-level modeling, and system-level integration across RTL, physical design, packaging and software teams.

This is a high-visibility position requiring frequent collaboration with internal teams and customers to define architectures that improve compute-per-watt for AI workloads and drive products from definition through production release.

Experience Level

Senior - typically 15–20 years of hands-on experience in SoC design, VLSI and systems architecture with multiple successful tapeouts.

Responsibilities

Primary responsibilities include architecture definition, modeling, integration and customer engagement.

• Own platform and micro-architecture definition, IP selection and KPI/PPA validation for Kepler products.
• Define architectures to improve memory bandwidth, capacity and energy efficiency for AI workloads.
• Develop high-level architectural and performance/power models to evaluate PPA and system throughput prior to RTL.
• Specify IP integration interfaces and align RTL, verification and physical design teams on timing and interfaces.
• Drive system-level integration with packaging and 3D innovation teams.
• Work across RTL, software, verification, physical design, packaging and DFX teams to ensure architectural decisions are implementable.
• Engage directly with customers on product definition and system-level reviews.
• Build and maintain performance and power estimation models and system-level simulators.
• Establish architecture best practices, review processes and documentation standards.
• Build, lead and mentor a team of architecture engineers and represent the team in customer, partner and executive reviews.

Requirements

Must-have technical skills, experience and competencies.

• 15–20 years of hands-on experience in SoC design, VLSI and systems architecture with multiple successful tapeouts.
• Deep expertise in SoC architecture, micro-architecture definition and high-level modeling.
• Strong experience with VLSI front-end flows: RTL, synthesis and timing and their interaction with physical design.
• Solid understanding of AI workloads, compute and memory access patterns and their hardware implications.
• Experience with memory architecture and integration and with high-performance, low-power VLSI methods.
• Knowledge of physical design, packaging and DFT/DFD principles; experience with 3D innovations.
• Experience with system design, validation, deployment and direct customer engagement.
• Strong modeling background (C/C++, SystemC/TLM) for performance and power estimation.
• Excellent leadership, communication and presentation skills and a proven record from architecture definition through production release.

Nice-to-have:

• Understanding of memory bandwidth and compute enhancement for memory-base die.
• Prior startup experience with lean teams and aggressive timelines.

Education Requirements

Required: B.Tech, M.Tech, MS or PhD in Electrical Engineering, ECE, Computer Engineering, Computer Science or a related technical field.

About the Company

Company: Keplercompute

Headquarters: San Jose, California, United States

Kepler is a semiconductor startup developing a new class of AI memory and logic using advanced materials and 3D architectures to build UHBM-based 3D-memory AI accelerator platforms. The team includes experienced semiconductor veterans and partners with foundries and customers to move lab technologies toward production.