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Principal Engineer, Signal Integrity

Marvell Technology
October 20, 2026
Full-time
On-site
Santa Clara, California, United States
$150,680 - $225,700 USD yearly
Other Semiconductor Jobs, Level - Senior

Job Title

Principal Engineer, Signal Integrity

Role Summary

Senior signal integrity engineer on the Platform Engineering team responsible for defining, analyzing, and verifying system interconnects for high-speed digital systems across board, switch, and optical platforms. The role provides SI/PI expertise, lab validation, and cross-functional technical leadership to meet performance, quality, and schedule targets.

Experience Level

Senior / Principal level. Typical experience guidance: 10–15 years; candidates with an advanced degree (Master's or PhD) may be considered with approximately 5–10 years of experience.

Responsibilities

Key responsibilities include technical ownership of system interconnects, simulation and lab verification, and cross-team/customer engagement.

  • Define and implement system interconnect specifications for board, switch, and optics platforms in partnership with circuit, packaging, and board teams.
  • Perform timing assessments and produce bump/RDL/package ballout specifications and reference routing guidelines.
  • Lead signal integrity delivery simulations using SI/PI tools and correlate simulation results with lab measurements and debug.
  • Support optical integration by evaluating board-to-module and module-to-switch signal paths for integrity and performance.
  • Develop SI/PI methodologies, rules, and workflows across high-speed traces and critical power domains.
  • Generate package and PCB models, run analyses and measurements, and provide design feedback and customer support for board reviews.
  • Mentor junior engineers and provide technical guidance on SI/PI practices.
  • Identify platform-level SI risks, propose mitigation strategies, and escalate issues to drive resolution.
  • Engage with customers on SI/PI specifications and support customer board-design reviews and analysis.
  • Role may require eligibility to access export-controlled technology; non-U.S. applicants may be subject to export license review.

Requirements

Must-have technical skills and experience; concise list below. Items noted as "Nice-to-have" are optional.

  • Strong understanding of electromagnetic fundamentals, transmission-line theory, via structures, high-speed connectors, and complex BGA packages.
  • Proficiency with 2D/3D EM and SI tools such as HFSS, Q3D, Sigrity Suite, ADS, and circuit simulators like HSPICE.
  • Hands-on experience with lab measurement and debug tools: oscilloscopes, vector network analyzers, and TDR.
  • Practical experience across board, switch, and optics platforms, including high-speed PCB layout, package technology, and optical module/interconnect integration.
  • Familiarity with high-speed interfaces such as DDR, PCIe, SerDes (25Gbps, 112G, 224G PAM4), USB, SATA, or similar.
  • Demonstrated ability to establish SI/PI parameters and design guidelines for board and package routing teams.
  • Customer-facing communication skills and experience supporting customer design reviews.
  • Strong analytical, problem-solving, and debug skills; ability to work under schedule pressure and drive issues to resolution.
  • Nice-to-have: experience setting up, running, and summarizing power integrity simulations.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field is stated with a typical experience range of 10–15 years. Advanced degrees (Master's or PhD in Electrical Engineering or related field) are noted and may be considered with approximately 5–10 years of experience.


About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.

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Date Posted: 2026-10-15