Principal Engineer, Power Integrity

Job Title

Principal Engineer, Power Integrity

Role Summary

Senior power integrity engineer on the Platform Engineering team responsible for PDN analysis, power plane design, verification, and lab validation across board, switch, and optics platforms. The role partners with circuit design, packaging, and board teams to define and implement power delivery solutions for high-speed, high-performance platforms.

Experience Level

Senior-level. Typical experience guidance: ~10–15 years for candidates with a Bachelor's degree; ~5–10 years for candidates with a Master's or PhD.

Responsibilities

Primary responsibilities include analysis, design, verification, and cross-team technical leadership for platform power delivery.

• Perform end-to-end PDN analysis across SoC package, board, and system-level power domains.
• Develop PDN target impedance specifications and decoupling capacitor strategies.
• Design and model power planes; generate package and PCB models for PI simulation and measurement correlation.
• Analyze VRM/regulator behavior, control-loop interactions, transient/load-step response, and voltage droop.
• Evaluate power delivery for optics integration and board-to-module/module-to-switch interfaces.
• Execute VNA and TDR lab measurements and correlate measurements with simulations.
• Develop PI methodologies, workflows, and rules for platform-level specifications.
• Provide technical guidance and mentor junior engineers on power integrity topics.
• Identify PI risks across the platform stack and define mitigation strategies.

Requirements

Must-have technical skills and tools for the role.

• Strong fundamentals in electromagnetics, transmission lines, and microwave theory relevant to PDN and high-speed signaling.
• Proficiency with PCB/package PI tools such as PowerSI, SIwave, or Cadence Sigrity.
• Experience with 2D/3D EM and circuit simulation tools (Ansys HFSS, HSPICE, ADS, COMSOL or similar).
• Hands-on experience with VNA and TDR measurements and common lab equipment (oscilloscopes, logic analyzers).
• Knowledge of decoupling capacitor placement strategies and AC impedance targets for board, switch, and optics platforms.
• Experience with EM field solvers and time/frequency domain tools for SoC, SerDes, and critical power-domain analysis.
• Understanding of EMI/EMC issues related to power delivery and debugging techniques.
• Ability to automate PI and packaging workflows using scripting (Python).
• Strong analytical and problem-solving skills and experience working in cross-functional programs.

Nice-to-have:

• Prior experience supporting customer board reviews and supplying customer-facing PI specifications.
• Experience developing PI rules and workflows for large platform programs (switches, optics, AI platforms).

Education Requirements

Bachelor's degree in Electrical Engineering or a related field with ~10–15 years of relevant experience; or Master's degree or PhD in Electrical Engineering or a related field with ~5–10 years of relevant experience. "Related field" includes comparable technical degrees relevant to power integrity, PCB/package, or high-speed design.

Compensation and Other Information

Expected base pay range (USD): 150,680 - 225,700 per year. Role is eligible for bonus and equity programs.

Reasonable Accommodation and Compliance

Applicants who require a reasonable accommodation during the selection process may contact Marvell HR Helpdesk at TAOps@marvell.com.

Export Compliance

This position may require access to technology or software subject to U.S. export control laws; applicants may be subject to export license review prior to employment.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.