Job Title
Principal Engineer, Physical Design
Role Summary
Lead physical-design execution for complex SoC programs from RTL-to-GDSII, owning timing, power, physical signoff, and verification to enable predictable first-pass silicon. Work within a cross-functional engineering organization (RTL, DFT, packaging, CAD, system teams) to meet performance, manufacturability, and schedule targets.
Experience Level
Senior-level. The posting specifies 12+ years of experience in physical design and signoff of complex, high-performance SoCs.
Responsibilities
Primary responsibilities to deliver production-quality silicon on aggressive schedules.
- Lead end-to-end RTL-to-GDSII flow: synthesis, floorplanning, placement, CTS, routing, and signoff.
- Develop and own timing, power, and physical signoff strategies including STA, SI, and IR/EM analysis.
- Establish and enforce DRC/LVS closure and physical verification methodologies; manage ECO flows for tapeout.
- Partner with RTL, DFT, packaging, and system teams to align design, testability, and manufacturability requirements.
- Define and deploy automation and design methodologies; develop scripts and collaborate with CAD to scale flows.
- Drive low-power design implementation (UPF/CPF) and integrate power-aware methodologies into the design flow.
- Communicate status and technical trade-offs to global stakeholders; support schedules and tapeout risk mitigation.
Requirements
Must-have technical skills and experience for this role.
- 12+ years of hands-on physical-design experience with successful tapeouts of complex SoCs at advanced nodes (28nm down to 5nm and below).
- Deep expertise in full-chip physical design: floorplanning, power planning, placement & routing, clock architecture/CTS, extraction, and signoff methodologies.
- Proficiency in scripting for automation (TCL, Python, Perl or similar) and experience partnering with CAD teams to improve flows.
- Strong cross-functional collaboration with RTL, DFT, packaging, product, and system engineering teams.
- Proven ability to define signoff strategy covering timing, signal/power integrity, and IR/EM to ensure high reliability.
- Excellent communication and stakeholder management skills in global engineering environments.
- Willingness to travel as required (listed as up to ~10%).
Education Requirements
B.Tech or M.Tech (or higher) in Electrical/Electronics Engineering or a related field.
About the Company
Company: Analog Devices
Headquarters: Norwood, Massachusetts, USA
Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.

Date Posted: 2026-05-27