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Principal Engineer – Physical Design

Microchip
May 19, 2026
Full-time
On-site
Chandler, Arizona, United States
Physical Design Jobs, Level - Senior

Job Title

Principal Engineer – Physical Design

Role Summary

Senior engineer on Microchip's CAD Physical Design (PD) team responsible for full-chip APR/physical implementation from netlist to GDSII. Work as part of a worldwide team on hierarchical, low-power, multi-mode, multi-corner mixed-signal designs to achieve timing, power, and physical sign-off.

Experience Level

Senior — requires 10+ years of relevant physical design experience.

Responsibilities

The role focuses on leading physical implementation activities and collaborating across geographically distributed teams to deliver production-ready designs.

  • Lead full-chip physical design (APR) efforts, including hierarchical and low-power flows.
  • Perform floorplanning, placement optimization, clock tree synthesis, routing, and crosstalk avoidance.
  • Drive timing closure, sign-off flows, and physical verification across process corners and modes.
  • Apply UPF/low-power design practices throughout the physical implementation flow.
  • Use sign-off tools for STA, formal equivalence, parasitic extraction, power integrity, and DRC/LVS.
  • Develop and maintain scripts and automation to improve flows and debug issues.
  • Collaborate with RTL, verification, sign-off, and product teams to resolve implementation issues.
  • Mentor junior engineers and provide technical leadership for project delivery.
  • Occasional travel (0–25%) to collaborate with other teams or sites.

Requirements

Must-have technical skills and experience.

  • 10+ years of hands-on experience in full-chip physical design and implementation.
  • Advanced knowledge of place-and-route methodologies and VLSI logic/timing principles.
  • Experience with timing closure, clock structures, and sign-off flows (STA, extraction, power integrity, physical verification).
  • Practical experience with UPF and low-power design practices throughout the physical flow.
  • Daily use of ICC/ICC2 or Cadence Innovus preferred.
  • Experience with 40nm or 28nm technologies required; 16nm or smaller preferred.
  • Proficiency in Tcl and Perl scripting for automation and flow development.
  • Strong problem-solving, debugging, and written/verbal communication skills.
  • Ability to work independently and collaborate across geographically distributed teams.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronics Engineering (or related field). The posting specifies a Bachelor’s or Master’s degree with 10+ years of relevant experience.


About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.

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Date Posted: 2026-05-19