Principal Engineer, Physical Design

Job Title

Principal Engineer, Physical Design

Role Summary

Lead physical design and methodology development for next-generation, high-performance processor/ASIC chips. Work across local and global teams to define RTL-to-GDSII implementation flows and enable scalable, high-performance silicon in advanced CMOS process nodes.

Experience Level

Senior — requires significant experience and technical leadership (seniority indicated by "Principal").

Responsibilities

Primary responsibilities include hands-on implementation, methodology leadership, and cross-team technical influence.

• Architect and lead development of physical design methodologies and automation flows.
• Own RTL-to-GDSII implementation tasks: synthesis, floorplanning, placement & routing, CTS, and timing closure.
• Provide deep technical guidance on static timing analysis and power/signal integrity flows.
• Collaborate with RTL, verification, CAD, and other cross-functional teams to resolve implementation issues.
• Mentor and coach senior and junior engineers; promote best practices across projects.
• Evaluate and drive adoption of emerging EDA tools and partner with internal CAD and external vendors.
• Represent the physical design team in strategic technical discussions and roadmap planning.

Requirements

Must-have:

• 10+ years of progressive experience in back-end physical design and verification, including leadership roles.
• Deep, practical experience with RTL-to-GDSII flows (synthesis, place & route, CTS, timing closure).
• Strong expertise in static timing analysis and power/signal integrity tools (examples: PrimeTime, Tempus, Voltus, RedHawk).
• Proficiency in scripting and automation (Python, Perl, Tcl, Makefile) for flow development.
• Demonstrated experience developing and deploying physical design methodologies and flows.
• Strong communication and collaboration skills; proven ability to mentor and influence cross-functional teams.

Nice-to-have:

• Experience evaluating and working with EDA vendors on tool adoption and integration.

Education Requirements

Bachelor's, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.