Principal Engineer – Physical Design

Job Title

Principal Engineer 6 Physical Design

Role Summary

The Principal Engineer will lead full-chip APR/physical implementation (netlist-to-GDSII) activities as part of Microchips CAD Physical Design team. This role supports hierarchical, low-power, multi-mode, multi-corner mixed-signal designs and coordinates with global teams to achieve sign-off-ready designs.

Primary mission: deliver and optimize physical implementation flows, ensure timing and power sign-off, and drive automation and methodology improvements for advanced process nodes.

Experience Level

Senior-level. The posting specifies 10+ years of relevant physical design experience.

Responsibilities

Key responsibilities include technical leadership of physical implementation, hands-on delivery, and cross-team collaboration.

• Lead full-chip APR/physical implementation tasks: floorplanning, placement optimization, clock tree synthesis, routing, and timing closure.
• Drive physical sign-off: static timing analysis, parasitic extraction, power integrity, formal equivalence, and physical verification.
• Implement and enforce UPF and low-power design practices across the physical design flow.
• Develop and maintain automation and scripts (Tcl, Perl) to improve flow efficiency and quality.
• Work with ICC/ICC2 or Innovus tools for daily implementation activities and debug complex routing/timing issues.
• Collaborate with RTL, synthesis, verification, and mixed-signal teams to meet multi-mode and multi-corner requirements.
• Mentor engineers, document flows, and contribute to methodology and tool selection decisions.
• Coordinate resolution of cross-domain issues to achieve sign-off on target process nodes.
• Travel as needed (0% 6 25%).

Requirements

Must-have technical skills and experience; a short list of preferred skills follows.

• 10+ years of hands-on experience in physical design flows, including floorplanning, placement, CTS, routing, and crosstalk avoidance.
• Advanced knowledge of place-and-route methodologies, VLSI timing closure, clock structures, and sign-off criteria.
• Experience with sign-off tools and flows: STA, formal equivalence, parasitic extraction, power integrity analysis, and physical verification.
• Practical experience implementing UPF and low-power design practices throughout the physical design flow.
• Proficiency in scripting for automation (Tcl and Perl required).
• Experience with 40 nm or 28 nm technologies (required); experience at 16 nm or smaller preferred.
• Strong written/verbal communication, problem-solving, and ability to collaborate across geographically distributed teams.

Nice-to-have:

• Daily use of ICC/ICC2 or Innovus (listed as preferred in the source).
• Experience improving flows and tool integrations for mixed-signal or multi-mode designs.

Education Requirements

Bachelor's or Masters degree in Electrical or Electronics Engineering is stated in the source. The posting also implies that equivalent practical experience may be acceptable given the explicit 10+ years of relevant experience requirement.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.