Principal Engineer - Memory Controller Design & Verification

Job Title

Principal Engineer - Memory Controller Design & Verification

Role Summary

Lead technical contributor responsible for design and verification of memory controller IP and related interfaces. Works with architects, RTL designers, verification engineers, and system teams to deliver robust, high-performance memory controller implementations.

Expected to drive verification strategy, debug complex issues, and mentor junior engineers while collaborating across silicon and software teams to achieve project milestones.

Experience Level

Senior (Principal) level. Typically a senior engineer with substantial hands-on experience in memory controller design and verification.

Responsibilities

Core responsibilities include technical leadership for memory controller projects and hands-on verification work.

• Define and execute verification strategy and test plans for memory controller IP.
• Develop and maintain verification environments (SystemVerilog/UVM or equivalent).
• Create directed and constrained-random tests, coverage models, and assertions.
• Debug RTL, simulation, and silicon bring-up issues; root-cause analysis and fixes.
• Collaborate with architects, RTL designers, and system engineers on interfaces and protocol support.
• Optimize performance, power, and area trade-offs for memory controller implementations.
• Mentor and guide junior engineers; drive best practices in design and verification.

Requirements

Must-have technical skills and desirable additions are listed below.

• Strong hands-on experience in memory controller verification and debug.
• Proficiency with SystemVerilog, UVM, assertions, and verification methodologies.
• Experience with DRAM protocols (e.g., DDR, LPDDR, HBM) and memory subsystem behavior.
• Familiarity with simulation, emulation, FPGA bring-up, and silicon validation flows.
• Proficiency in scripting and automation (Python, Perl, Tcl or similar).
• Solid RTL understanding and digital design fundamentals (timing, pipelining, interfaces).
• Good communication skills and experience collaborating across cross-functional teams.
• Nice-to-have: experience with protocol bridges, PHY integration, performance modeling, or prior role leading verification teams.

Education Requirements

Not specified.

About the Company

Company: Rambus

Headquarters: Sunnyvale, California, USA

Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.