Principal Engineer - Memory Controller Design Verification
Senior/Principal design verification engineer for the Memory Controller IP team, focused on pre-silicon RTL verification of DDR, HBM, and GDDR controller technologies. The role reports to the local onsite manager and works in a hybrid onsite/remote model.
The primary mission is to develop and execute verification strategies, testbenches, and regression suites to ensure correctness and quality of memory controller RTL.
Senior / Principal level. The posting specifies a minimum of 7 years of HDL design-verification experience.
Key technical responsibilities include verification planning, test development, and support of verification infrastructure.
Must-have technical skills and experience; preferred items listed separately.
Bachelor's degree or higher in Electrical Engineering, Computer Science, or a closely related technical field. (The posting specifies "Bachelors Degree or above in EE/CS".)
Company: Rambus
Headquarters: Sunnyvale, California, USA
Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.
