Principal Engineer, High-Speed RTL Design

Job Title

Principal Engineer, High-Speed RTL Design

Role Summary

Design and implement timing-critical RTL for high-speed memory and SoC interfaces. Deliver nanometer-process-aware, clocking/reset/power-aware RTL and collaborate with verification, synthesis, and integration teams to achieve timing closure and reliable operation.

Role is part of the RTL engineering organization in Bengaluru and focuses on high-performance, latency-sensitive control and datapath logic.

Experience Level

Senior (Principal). Specific years of experience not specified.

Responsibilities

Primary duties include RTL design, integration, verification support, and documentation.

• Design and implement timing-critical RTL blocks: control and sequencing FSMs, power-up/shutdown/mode-transition logic, register banks, configuration logic, telemetry and monitoring datapath.
• Develop RTL with attention to latency, deterministic behavior, race-free logic, and metastability avoidance.
• Write nanometer-process-aware RTL robust to tight setup/hold margins, clock skew and uncertainty, multi-cycle and false-path constraints, and PVT variation.
• Ensure RTL is clean for synthesis, static timing analysis, and ECO cycles in advanced technology nodes.
• Implement and review clock-domain crossings using proven synchronization techniques; design reset and initialization logic for predictable startup and recovery.
• Support power-aware and mode-dependent behavior as required by system operation.
• Integrate RTL blocks into larger subsystems or top-level designs and resolve port-list mismatches, clock/reset dependencies, and mode interaction issues.
• Debug RTL and integration issues using simulation waveforms and tool feedback.
• Work closely with verification engineers to clarify design intent, fix RTL issues, and address timing issues identified during synthesis or place-and-route.
• Participate in design/RTL reviews and maintain clear documentation of block functionality, assumptions, and known limitations.

Requirements

Must-have technical skills and flow awareness.

• Strong proficiency in SystemVerilog/Verilog RTL.
• Experience with FSM design and implementation, reset synchronization, and clock-domain crossing concepts.
• Solid understanding of setup/hold timing fundamentals, critical-path sensitivity, and timing-critical control logic.
• Familiarity with RTL lint and CDC checks, synthesis flow, and interpreting basic static timing analysis (STA) reports.
• Experience with DFT-friendly RTL practices, UPF, and LEC; ability to support RTL sign-off and late integration debug.
• Ability to refine logic to address timing issues, including simplifying control paths and adding limited pipelining under guidance.
• Strong debugging skills using simulation and tool feedback; effective collaboration with verification and physical design teams.
• Works independently on assigned modules or subsystems and demonstrates ownership of RTL quality and delivery.

Nice-to-have: Experience with PMICs or mixed-signal SoCs, exposure to industry-standard specifications, basic scripting (Python/Tcl), and experience applying AI-enabled engineering tools.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.