Principal Engineer – HBM Design for Test (DFT)

Job Title

Principal Engineer – HBM Design for Test (DFT)

Role Summary

The Principal Engineer for HBM Design for Test (DFT) is a senior technical contributor responsible for defining, deploying, and sustaining DFT architecture and solutions across HBM core and base die families. The role focuses on specification ownership, alignment with cross-functional teams, and program support through tape‑out and silicon bring‑up.

Experience Level

Senior — typically 8+ years of relevant semiconductor experience.

Responsibilities

Primary responsibilities center on DFT architecture, specification ownership, and ensuring manufacturable, testable HBM products.

• Own and implement DFT architecture and feature intent for assigned domains across HBM core and base die.
• Ensure DFT solutions support high quality, low cost, and manufacturability for HBM products.
• Translate manufacturing and test needs into clear DFT requirements and test modes.
• Align spec-to-verification coverage with DFT verification teams to ensure readiness for tape‑out and bring‑up.
• Identify and resolve DFT-related issues during build execution, tape‑out, and silicon bring‑up.
• Serve as the DFT point of contact for assigned programs or functional areas.
• Drive standardization and reuse of DFT features across HBM families.
• Participate in DFT governance, design and verification readiness reviews.
• Contribute to documentation, knowledge sharing, and training within the DFT organization.

Requirements

Must-have technical skills and experience for immediate contribution.

• 8+ years of semiconductor development experience with exposure to DFT, verification, test strategy, manufacturability, or silicon debug.
• Proven experience defining and influencing DFT requirements, specifications, and verification expectations.
• Working knowledge of memory architectures; HBM or DRAM experience preferred.
• Experience partnering with design engineering, product engineering, test, and verification organizations to deliver testable solutions.
• Demonstrated ability to resolve cross-functional issues through execution to tape‑out and silicon bring‑up.
• Strong problem-solving skills and ability to drive standardization and reuse.

Nice-to-have:

• Experience owning DFT architecture across multiple product families.
• Prior involvement in DFT governance and readiness reviews.
• Strong written and verbal communication and multi‑functional collaboration skills.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field is required; Master’s degree is preferred. (No explicit equivalent‑experience statement provided.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.