Principal Engineer, Hardware-Assisted Verification (Embedded Firmware & FPGA)

Job Title

Principal Engineer, Hardware-Assisted Verification (Embedded Firmware & FPGA)

Role Summary

Lead the architecture and delivery of hardware-assisted verification (HAV), simulation acceleration, and hybrid verification solutions for large-scale SoCs and multi-die systems. The role partners with R&D, Product Management, and Applications teams to define verification strategies and influence product roadmaps.

Primary mission: accelerate customer verification cycles, enable earlier software and system bring-up, and scale reusable verification assets across strategic accounts.

Experience Level

Level: Senior — typically 10+ years of experience in SoC verification, emulation, or system-level validation.

Responsibilities

Deliver technical leadership for HAV and acceleration across internal teams and customer deployments.

• Architect and lead HAV, simulation acceleration, and prototyping solutions for complex SoCs and multi-die systems.
• Define and own system-level verification and acceleration strategies spanning simulation, emulation, and prototyping.
• Bridge RTL simulation, emulation, and software bring-up to enable early and scalable system validation.
• Lead complex customer engagements and act as a technical authority in escalations and adoption.
• Translate customer verification challenges into scalable, reusable solution architectures.
• Drive innovation in methodologies, automation, reuse, and productivity frameworks; evaluate AI/GenAI-assisted approaches.
• Collaborate with R&D, product management, and applications teams to influence product roadmaps and feature requirements.
• Mentor and empower senior engineers and influence cross-functional teams on best practices and roadmaps.

Requirements

Core qualifications and skills required to perform the role.

Must-have:

• 10+ years of experience in SoC verification, emulation, or system-level validation.
• Deep hands-on expertise in hardware-assisted verification, simulation acceleration, and hybrid verification flows.
• Strong experience with emulation platforms and accelerated simulation environments.
• Solid understanding of SoC architectures, interconnects, memory subsystems, and software bring-up challenges.
• Proven ability to design and deploy scalable verification solutions and reusable assets for complex designs.
• Experience with system-level testbenches, transactors, and acceleration frameworks.
• Track record of influencing product direction or defining solution roadmaps.

Nice-to-have:

• Exposure to AI/GenAI techniques applied to verification, debug, or automation.
• Background in high-speed interfaces, memory subsystems, or multi-die architectures.
• Experience leading strategic customer engagements and mentoring distributed engineering teams.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.