Principal Engineer, Edge NPU Engineering

Job Title

Principal Engineer, Edge NPU Engineering

Role Summary

Lead definition and delivery of high-performance, low-power Neural Processing Unit (NPU) architectures for edge AI and LLM inference. Work across architecture, hardware/software co-design, compiler/toolchain enablement, and system-level performance tuning within an NPU/SoC engineering team.

Enable efficient execution of small and medium LLMs on resource-constrained edge devices by building scalable AI acceleration solutions, integrating hardware and software components.

Experience Level

Senior level. The posting requires more than 3 years of relevant experience in AI accelerators, NPU, GPU, DSP, or heterogeneous compute architecture and expects substantial architecture and system-level expertise.

Responsibilities

Primary responsibilities include architecture design, cross-team collaboration, and toolchain enablement for NPU-based edge AI platforms.

• Define and architect high-performance, low-power NPU cores for edge AI and LLM inference.
• Evaluate and integrate open-source NPU architectures and AI acceleration frameworks.
• Drive hardware/software co-design for transformer and LLM workloads, including KV cache handling and attention acceleration.
• Optimize for memory bandwidth efficiency, sparse computation, and quantized models (INT8/INT4/FP8).
• Design scalable compute and memory subsystem architectures and dataflow.
• Collaborate with RTL, compiler, SDK, and AI software teams to enable end-to-end AI execution.
• Build and optimize compiler, runtime, kernel libraries, model conversion tools, and profiling/debugging infrastructure.
• Enable popular AI frameworks and LLM runtimes on the NPU platform.
• Analyze workload bottlenecks and optimize system-level power/performance/area (PPA).
• Contribute to AI architecture roadmap and work with system architects on heterogeneous integration (CPU, NPU, memory, interconnect).
• Travel approximately 10% as required.

Requirements

Key technical must-haves and preferred skills.

• Must-have: More than 3 years experience in AI accelerator, NPU, GPU, DSP, or heterogeneous compute architecture; deep knowledge of transformer architectures, LLM inference, neural network acceleration, memory hierarchy optimization, and dataflow architecture.
• Must-have: Experience with AI model optimization techniques such as quantization, pruning, sparsity, and operator fusion.
• Must-have: Solid hardware/software co-design experience and familiarity with compiler and runtime stacks for AI acceleration; experience with RTL architecture and performance modeling.
• Must-have: Strong programming skills in C/C++, Python, or similar languages.
• Nice-to-have: Experience with high-performance RISC-V CPU architecture or SoC design; experience with vector processors, SIMD/SIMT, or AI instruction extensions.
• Nice-to-have: Familiarity with MLIR, TVM, ONNX, LLVM or other AI compiler frameworks; experience with chiplet, NoC, advanced memory architectures, or open-source AI acceleration ecosystems.
• Nice-to-have: Experience enabling LLMs on edge/embedded platforms and low-power SoC/mobile AI optimization.

Education Requirements

MS or PhD in Computer Engineering, Electrical Engineering, Computer Science, or a related field (posting specifies MS or PhD).

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.