Principal Engineer - Ecosystem IP Quality

Job Title

Principal Engineer - Ecosystem IP Quality

Role Summary

As part of the IP Quality team, the Principal Engineer qualifies and validates third-party and internal semiconductor IP for compatibility with GF process design kits (PDKs) and customer tape-outs. The role coordinates incoming IP assessments, drives IP regression testing, and resolves technical issues with vendors and internal teams to ensure successful integration and delivery.

Experience Level

Senior - minimum 10 years' experience in IC design or semiconductor IP qualification.

Responsibilities

Primary responsibilities include IP qualification, regression testing, documentation, and stakeholder coordination to support customer tape-outs.

• Perform incoming IP QA against a predefined checklist; verify DK and silicon deliverables and issue certificates of approval or non-conformance.
• Qualify IP merge kits to support customer tape-outs and maintain IP catalog entries and databases.
• Define comprehensive IP qualification and regression test cases; execute regressions (physical verification DRC/LVS/DFM, PEX extraction, Spice simulation) against passing criteria.
• Assess IP impact from PDK/process updates and consolidate assessment results.
• Chair technical reviews with stakeholders and drive defects/issues to closure.
• Maintain IP regression and SOP workflow documentation; prepare materials for audits and ensure EHSS compliance.
• Automate and script workflows to improve efficiency; document technical issues, waivers, and assessment reports.
• Support customer technical queries related to IP.

Requirements

Must-have technical skills and experience:

• Proficient in SystemVerilog/Verilog and simulation-based verification; experience developing verification methodology for complex circuits.
• Experience with DFT: scan insertion, ATPG, and functional test vector development.
• Hands-on experience with industry-standard EDA/CAD tools and performing IP regression (DRC/LVS/DFM, PEX extraction, Spice simulation).
• Experience with PHY co-simulation (RTL + SPICE) in Cadence co-sim environments and debugging Verilog testbenches.
• Ability to create test plans, maintain IP/regression databases, consolidate results, and drive remediation with vendors and stakeholders.
• Scripting and automation skills to improve workflows (e.g., Python, TCL).

Nice-to-have:

• Knowledge of Tetramax models and ATPG coverage.
• RF design experience.
• Additional experience in physical layout, process-aware design, and advanced physical verification.

Education Requirements

Bachelor's or Master's degree in Electrical or Electronics Engineering (or equivalent). The posting indicates equivalent practical experience is acceptable.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.