Principal Engineer, Digital IC Design
Senior ASIC engineer responsible for planning, coordinating and executing the design, verification and evaluation of analog mixed-signal circuits—primarily SerDes PHY IP—for high-speed data communication ICs. The role works within the Central Engineering AMS-IP team and collaborates with digital design, verification, firmware and analog teams to deliver IP across product lines.
You will drive delivery of competitive SerDes IP by managing technical execution, cross-functional coordination, and post-silicon support.
Senior — typical experience ranges: 10–15 years with a Bachelor’s degree, or 5–10 years with a Master’s degree or PhD.
Primary responsibilities include leading technical execution and coordinating cross-discipline activities to deliver analog mixed-signal IP on schedule and to quality targets.
Must-have technical skills and professional competencies required for the role.
Nice-to-have:
Bachelor's degree in Computer Science, Electrical Engineering or related field (typical experience 10–15 years). Alternatively, a Master's degree or PhD in Computer Science, Electrical Engineering or related field (typical experience 5–10 years). The posting specifies these degree fields; equivalent relevant experience is implied by the stated experience ranges.
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
