Principal Engineer, DFT - SoC Engineering

Job Title

Principal Engineer, DFT - SoC Engineering

Role Summary

Hands-on DFT principal engineer responsible for owning DFT architecture, implementation, integration, and verification for complex SoCs and subsystems from specification through tapeout. The role works directly with customer and internal design teams and collaborates across RTL design, verification, physical implementation, and test engineering.

Primary mission: ensure testability, maximize coverage and yield, reduce production test cost/time, and create reusable DFT methodologies that enable first-pass silicon success.

Experience Level

Senior — typically 10+ years of hands-on SoC DFT experience.

Responsibilities

Primary responsibilities include defining and executing DFT strategy, driving signoff readiness, and supporting post-silicon debug and production test improvements.

• Own DFT architecture, implementation, integration, and verification for complex SoCs/subsystems from specification through tapeout.
• Define and execute test strategies across scan/ATPG, memory BIST, logic BIST, and analog/PHY test considerations to meet coverage, quality, yield, and cost targets.
• Drive DFT signoff readiness by identifying testability risks early, proposing design changes, and ensuring closure across the RTL-to-GDS flow.
• Develop and institutionalize reusable DFT methodologies, checklists, and guidelines; apply Synopsys EDA tools to solve customer problems on active projects.
• Partner with silicon validation and test engineering teams on post-silicon debug, failure analysis triage, and pattern refinement.
• Collaborate with RTL design, functional verification, physical design, timing, and power teams to ensure testability from architecture through signoff.
• Provide technical guidance through design reviews, integration/debug support, and best-practice sharing (individual contributor role).

Requirements

Must-have skills and experience for successful performance in this role.

• Typically 10+ years of hands-on SoC DFT experience with proven depth in scan/ATPG, memory BIST, logic BIST, and analog test considerations.
• Demonstrated experience owning DFT implementation for complex SoCs that have taped out and gone to production.
• Strong understanding of the end-to-end SoC design flow: microarchitecture → RTL → verification → synthesis → timing/physical implementation → signoff.
• Proven ability to work cross-functionally to resolve testability issues and drive closure under schedule constraints.
• Post-silicon debug experience and collaboration with test engineering teams to refine production test programs (preferred).
• Familiarity with Synopsys DFT tools such as TetraMAX, DFT Compiler, and/or BIST Architect (preferred).
• Strong communication skills; able to translate DFT tradeoffs into schedule/cost/yield impact for stakeholders.

Education Requirements

Bachelor's or Master’s degree in Electronics Engineering, Electrical Engineering, or a related field; equivalent practical experience acceptable where demonstrated by hands-on SoC DFT tapeout and production experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.