Principal Engineer - DFT

Job Title

Principal Engineer - DFT

Role Summary

Lead DFT architecture, implementation, and methodology for Ambiq's ultra-low-power SoC portfolio. Serve as a hands-on technical authority across the full DFT lifecycle—architecture, RTL integration, scan insertion, ATPG, MBIST, verification, silicon bring-up, and production test—working closely with RTL, STA, physical design, verification, and test engineering teams.

This is an onsite role based in NW Austin, TX, requiring regular presence at the Austin site.

Experience Level

Senior. The role typically requires 15+ years of progressive, hands-on DFT implementation and architecture experience with complex SoCs.

Responsibilities

Hands-on technical leadership and delivery of DFT solutions across multiple concurrent SoC programs.

• Lead DFT architecture and methodology for blocks, subsystems, and full-chip SoCs.
• Implement and optimize scan insertion, scan compression, stuck-at, at-speed, and path-delay tests.
• Develop and run ATPG flows, debug patterns, and close coverage gaps to meet test and manufacturing objectives.
• Design and validate MBIST architecture, memory test patterns, and memory repair flows.
• Perform pre-layout and post-layout gate-level simulations for ATPG/MBIST verification.
• Coordinate with RTL teams to resolve logic and architectural DFT issues; trace problems from gate-level to RTL.
• Work with STA and physical design to resolve DFT timing, clocking, congestion, power, and implementation issues.
• Define and review timing constraints (SDC) for scan, ATPG, MBIST, and test modes.
• Support silicon bring-up, production test program development, and pattern deployment.
• Analyze ATE failure data and perform ATPG-based diagnosis and root-cause analysis.
• Develop automation and infrastructure using Tcl, Python, Perl, or similar scripting languages.
• Drive continuous improvement of DFT flows, automation, and best practices; mentor and provide technical guidance to other engineers.

Requirements

Key required skills and practical experience for immediate contribution and leadership.

• Extensive hands-on experience with Cadence Genus and Cadence Modus Compression (required).
• Deep expertise in scan insertion, ATPG, scan compression, stuck-at, at-speed, path-delay, boundary scan, and JTAG.
• Proven experience with Tessent MBIST for memory test architecture, pattern generation, verification, and memory repair.
• Strong low-power DFT experience, including power-aware scan and ATPG methodologies.
• Practical RTL design and debug skills sufficient to trace DFT issues back to RTL.
• Extensive knowledge of STA, timing concepts, SDC constraints, clocking, and test-mode timing closure.
• Experience developing ATPG and MBIST testbenches and performing gate-level simulations.
• Experience supporting silicon bring-up, production test programs, and analyzing ATE failure data.
• Strong scripting and automation skills (Tcl, Python and/or Perl).
• Proven ability to lead technical direction, mentor engineers, and remain hands-on in implementation.

Nice-to-have:

• Experience developing DFT for ultra-low-power MCUs/SoCs and multi-voltage/multi-power-domain designs.
• Experience with power-aware ATPG, scan-power optimization, and IR-drop considerations during test.
• Experience establishing or significantly improving DFT architecture, automation, or methodology across a product portfolio.
• Experience supporting multiple SoC programs or product families concurrently.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related technical field.

About the Company

Company: Ambiq

Headquarters: Austin, TX, United States

Semiconductor company developing ultra-low-power microcontroller units (MCUs) and system-on-chip (SoC) platforms for battery-powered and edge devices, focusing on low-power IP, RTL, and production silicon solutions.