Principal Engineer DFT

Job Title

Principal Engineer DFT

Role Summary

Lead DFT architecture and implementation for mixed-signal SoCs, defining test access, scan, MBIST/LBIST, and boundary-scan strategies. Work across RTL, physical design, verification, test, probe, and manufacturing teams to ensure testability, diagnosability, and successful silicon bring-up.

Experience Level

Senior — typically requires 10+ years of relevant SoC design or DFT experience.

Responsibilities

Primary responsibilities include:

• Own DFT implementation including scan, MBIST, LBIST, boundary scan (JTAG), and test access architectures for mixed-signal SoCs.
• Define DFT architecture early in the design cycle and align it with SoC integration, floorplanning, timing, power, and physical design constraints.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels in collaboration with RTL and integration teams.
• Execute DFT flows and lead signoff activities: lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design to optimize DFT for placement, routing, timing closure, and DRC/LVS signoff.
• Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up, ATE testing failure debug, and yield/debug analysis.
• Partner with CAD and methodology teams to define, improve, and standardize DFT flows across SoC programs.

Requirements

Must-have skills and experience:

• 10+ years of experience in SoC design, DFT, or implementation for complex digital ASICs/SoCs.
• Hands-on experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
• Familiarity with full RTL-to-GDS flows and interactions between DFT, synthesis, STA, and physical design.
• Proficiency with industry-standard EDA tools for DFT and implementation (examples: Synopsys, Cadence, Siemens).
• Scripting skills for flow automation (Python, Tcl, Perl, etc.).
• Experience executing DFT flows and performing signoff checks (lint, CDC, DFT rule checks) and coverage closure.
• Experience supporting post-silicon failure analysis and ATE testing failure debug.

Nice-to-have:

• Experience with Analog-Mixed-Signal SoCs and multi-IP subsystem integration.
• Experience partnering with CAD/methodology teams to standardize flows across programs.
• Familiarity with using approved AI tools to augment DFT activities and improve execution efficiency.

Education Requirements

Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.