Principal Engineer, Design Verification Engineering

Job Title

Principal Engineer, Design Verification Engineering

Role Summary

Lead verification for complex digital SoCs and subsystems within a multifunctional engineering team. Own verification strategy, architecture, methodology and execution from planning through signoff while coordinating with architecture, design, emulation, FPGA, firmware, and software teams.

Experience Level

Senior-level — 12+ years of experience in digital pre-silicon verification with demonstrated leadership across IP, subsystem, or SoC-level DV.

Responsibilities

Key responsibilities include:

• Lead end-to-end SoC verification from planning to signoff, including test planning and coverage closure.
• Architect and implement scalable UVM-based testbenches, DV flows, and verification methodologies.
• Verify microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification techniques.
• Drive pre-silicon readiness with emulation, FPGA, and software teams to address post-silicon scenarios early.
• Apply formal verification and perform NoC/interconnect and system-level performance verification.
• Define and review test plans; ensure functional and code coverage closure at block, subsystem, and SoC levels.
• Collaborate cross-functionally with architecture, RTL, firmware, and system teams to ensure full-system correctness.
• Mentor and provide technical leadership to verification engineers and drive verification innovation and process improvements.

Requirements

Must-have skills and experience:

• Strong SoC/subsystem architecture knowledge and hands-on Verilog/SystemVerilog experience.
• Proven expertise with UVM-based testbench development, constrained-random verification, and assertions.
• Experience closing verification using functional and code coverage metrics across multiple levels.
• NoC, bus, and interconnect verification experience and coverage analysis/optimization skills.
• Experience in architecting scalable testbench environments and defining robust DV flows.
• Power-aware verification experience (UPF) and power analysis/optimization skills.
• Practical experience with formal verification and flow definition for connectivity and property checking.
• Protocol verification experience (I2C, SPI, Ethernet, UART, AXI/AHB, DMA, SVI3) and familiarity with gate-level simulation with timing annotation.
• Proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell); familiarity with processor platforms (ARM, RISC-V, Tensilica) and AI/ML accelerators.
• Strong communication, leadership, and problem-solving skills; willingness to travel approximately 10%.

Education Requirements

B.Tech or M.Tech in a relevant engineering discipline (for example Electrical, Electronics, Computer Science) and 12+ years of experience in digital pre-silicon verification.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.