Principal Engineer, Design Verification Engineering

Job Title

Principal Engineer, Design Verification Engineering

Role Summary

Lead pre-silicon verification for complex SoCs and subsystems, define verification architecture and strategy, and drive verification from planning through signoff. Work within a multifunctional team and collaborate with architecture, design, emulation/FPGA, firmware and software teams to ensure full-system correctness and delivery.

This role focuses on scalable UVM-based testbenches, formal and emulation flows, coverage closure, and verification methodologies across block, subsystem and SoC levels.

Experience Level

Senior - requires extensive experience; the posting specifies 12+ years of digital pre-silicon verification and leadership experience.

Responsibilities

Lead verification activities and deliverables for large integrated digital products.

• Plan and execute end-to-end SoC verification from strategy to signoff.
• Architect and implement scalable UVM-based testbenches and DV flows.
• Define verification plans and ensure closure of functional and code coverage at block, subsystem and SoC levels.
• Verify microprocessor-based designs, AI/ML accelerators, and high-speed peripherals.
• Coordinate pre-silicon readiness with emulation, FPGA, firmware, and software teams.
• Apply formal verification techniques for IP and subsystem validation.
• Lead NoC/interconnect verification and system-level dataflow validation.
• Perform performance verification and system-level analysis using realistic use cases.
• Mentor and technically lead team members; drive verification methodology improvements and cross-group initiatives.

Requirements

Must-have technical skills and experience for successful execution of the role.

• Extensive hands-on experience in digital pre-silicon verification at IP, subsystem or SoC level, including leadership roles.
• Proficient in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.
• Proven ability to achieve verification closure using functional and code coverage metrics.
• Expertise in NoC, bus and interconnect verification, and coverage analysis.
• Experience with power-aware verification (UPF) and power analysis.
• Hands-on experience with formal verification flows and property checking.
• Protocol verification experience for interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA and SVI3.
• Familiarity with gate-level simulation with timing annotation (GLS).
• Understanding of processor-based systems (ARM, RISC-V, Tensilica) and AI/ML accelerators.
• Proficiency in C/C++, SystemC and scripting (Python, TCL, Shell) for verification and automation.
• Strong communication, leadership, cross-functional collaboration and problem-solving skills.
• Nice-to-have: exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY).

Education Requirements

B.Tech or M.Tech (as stated in the posting).

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.