Principal Engineer - Design Verification Engineering

Job Title

Principal Engineer - Design Verification Engineering

Role Summary

Lead the pre-silicon design verification effort for complex SoCs and subsystems. Provide technical leadership to a verification team, define verification architecture and strategy, and collaborate with architecture, design, emulation, FPGA, firmware and system teams to drive verification to signoff.

Work focuses on scalable UVM-based environments, coverage-driven closure, formal techniques, and system-level validation for integrated products.

Experience Level

Senior — Principal level. The role references 12+ years of experience in digital pre-silicon verification and leadership across IP, subsystem, or SoC-level DV.

Responsibilities

Deliver end-to-end verification and lead the team through planning, execution, and signoff.

• Lead SoC and subsystem verification from strategy and planning through signoff.
• Architect and implement scalable UVM-based testbenches and DV flows.
• Define verification plans and ensure closure of functional and code coverage at block, subsystem, and SoC levels.
• Verify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals.
• Integrate pre-silicon efforts with emulation, FPGA, and software teams to cover system use cases early.
• Apply formal verification techniques for IP and subsystem validation.
• Lead NoC/interconnect verification and perform performance and system-level analysis.
• Mentor engineers, provide technical leadership, and drive verification methodology improvements across teams.

Requirements

Key must-have skills, technologies, and capabilities for the role.

• Extensive hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.
• Proven track record in coverage-driven verification closure and test planning.
• Experience with NoC, bus, and interconnect verification and coverage optimization.
• Power-aware verification experience (UPF) and power analysis knowledge.
• Hands-on experience with formal verification: flow definition, connectivity checks, and functional property verification.
• Protocol verification experience for interfaces such as AXI/AHB, Ethernet, I2C, SPI, UART, DMA, SVI3.
• Familiarity with gate-level simulations with timing annotation (GLS) and constrained-random verification, assertions, and transaction-level modeling.
• Proficiency in processor-based systems (ARM, RISC-V, Tensilica), and programming/scripting in C/C++, SystemC, Python, TCL, Shell.
• Strong communication, leadership, and cross-functional collaboration skills.
• Willingness to travel approximately 10% for role-related activities.

Nice-to-have:

• Exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY).
• Experience with emulation, portable stimulus, and virtual platform techniques.
• Security and functional-safety verification experience.

Education Requirements

B.Tech or M.Tech in a technical discipline (e.g., Electrical/Electronics/Computer Engineering or related) as specified in the posting; the role references 12+ years of relevant digital pre-silicon verification experience.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.