Principal Engineer, Design Verification Engineering

Job Title

Principal Engineer, Design Verification Engineering

Role Summary

Lead design verification for complex digital SoCs and subsystems. Responsible for verification strategy, architecture, methodology, and driving pre-silicon verification from planning through signoff across IP, subsystem, and SoC levels.

Work within a multifunctional team and collaborate with architecture, design, emulation, FPGA, firmware and system teams to ensure full-system correctness and silicon readiness.

Experience Level

Senior — Principal-level individual contributor/technical leader. The posting specifies approximately 12+ years of experience in digital pre-silicon verification and leadership across IP, subsystem, or SoC-level DV.

Responsibilities

Key responsibilities include:

• Lead end-to-end SoC verification efforts from planning to signoff for complex digital SoCs.
• Verify microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced methodologies.
• Define verification architecture, flows, and scalable UVM-based testbenches; implement DV methodologies and environments.
• Plan and track team execution; provide technical leadership, mentoring, and guidance.
• Collaborate with architecture and design teams to define requirements and align verification deliverables and dependencies.
• Coordinate with emulation, FPGA, and software teams to cover post-silicon scenarios early and drive pre-silicon readiness.
• Develop and execute system-level use cases for functional validation and perform performance verification.
• Define and review test plans; ensure closure of functional and code coverage at block, subsystem, and SoC levels.
• Apply formal verification techniques and lead NoC/interconnect verification to ensure robust data flow across the SoC.
• Drive verification innovation using formal, emulation, portable stimulus, and virtual platform techniques.

Requirements

Must-have skills and experience:

• Strong understanding of SoC/subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.
• Proven track record achieving verification closure using functional and code coverage metrics across block, subsystem, and SoC levels.
• Expertise in NoC, bus, and interconnect verification, including coverage analysis and optimization.
• Experience architecting scalable testbench environments and defining robust DV flows and methodologies.
• Power-aware verification experience (UPF), including power analysis and optimization.
• Hands-on experience with formal verification (flow definition, connectivity, functional property checking).
• Protocol verification experience for interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.
• Experience in security and safety verification and familiarity with gate-level simulations with timing annotation (GLS).
• Strong skills in test planning, constrained-random verification, assertions, and transaction-level modeling.
• Good understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators; proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).
• Excellent communication, leadership, and cross-functional collaboration skills; strong problem-solving mindset.
• Willingness to travel (~10% as noted).
• Nice-to-have: exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY).

Education Requirements

The posting specifies B.Tech or M.Tech degrees (engineering). The posting also indicates ~12+ years of relevant pre-silicon verification experience.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.