Principal Engineer, Design Verification Engineering

Job Title

Principal Engineer, Design Verification Engineering

Role Summary

Lead verification of complex digital SoCs and subsystems in a multifunctional team. Responsible for verification strategy, architecture, methodology, and delivery across pre‑silicon verification activities to achieve signoff quality and schedule.

Work with architecture, design, emulation, FPGA, firmware, and software teams to ensure system-level correctness and pre‑silicon readiness.

Experience Level

Senior - requires 12+ years of experience in digital pre‑silicon verification and proven leadership across IP, subsystem, or SoC verification.

Responsibilities

Primary duties include planning and executing verification activities, defining methodology, and driving team delivery for large integrated products.

• Lead end-to-end SoC verification from planning through signoff.
• Verify microprocessor-based subsystems, AI/ML accelerators, and high-speed peripherals.
• Architect and implement scalable UVM-based testbenches and DV flows.
• Define test plans and drive functional and code coverage closure across block, subsystem, and SoC levels.
• Coordinate with emulation, FPGA, firmware, and software teams for pre-silicon readiness and system-level validation.
• Apply formal verification techniques and perform NoC/interconnect verification.
• Conduct power-aware verification (UPF), performance verification, and system-level analysis.
• Mentor and lead engineers, plan tasks, track progress, and contribute to verification methodology improvements.

Requirements

Must-have technical skills and experience for successful execution of the role.

• Extensive hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development and debugging.
• Proven track record of verification closure using functional and code coverage metrics.
• Experience with NoC, bus, and interconnect verification, including coverage analysis and optimization.
• Formal verification experience (flow definition, connectivity, property checking).
• Knowledge of power-aware verification (UPF) and gate-level simulations with timing annotation.
• Protocol and interface verification experience: I2C, SPI, Ethernet, UART, AXI/AHB, DMA, SVI3.
• Familiarity with processor-based systems (ARM, RISC‑V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).
• Strong communication, leadership, and cross-functional collaboration skills.
• Nice-to-have: exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY), security and safety verification, emulation, and portable stimulus.

Education Requirements

Requires a B.Tech or M.Tech degree. The job posting specifies B.Tech/M.Tech and expects 12+ years of experience in digital pre‑silicon verification.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.