Principal Engineer, Design Verification - DDR Memory Subsystems

Job Title

Principal Engineer, Design Verification - DDR Memory Subsystems

Role Summary

Lead technical verification efforts for next-generation DDR memory subsystem IP integrated into Altera FPGA products. Serve as the verification authority for memory controllers, PHYs, training/calibration flows, and subsystem integration across multiple product generations.

The role partners with architecture, RTL, physical design, firmware, system validation, and silicon teams to define verification strategy, drive closure, and support post-silicon bring-up.

Experience Level

Senior — Principal-level engineering role. The posting requests 15+ years of design verification experience and 10+ years verifying DDR memory subsystems.

Responsibilities

Primary responsibilities include technical leadership of verification programs and delivery of robust, reusable verification environments and methodologies.

• Serve as technical lead for design verification of complex DDR memory subsystems across FPGA product families.
• Define and drive verification architecture, methodology, and strategy for controllers, PHYs, training, calibration, and subsystem integration.
• Architect scalable, reusable UVM/SystemVerilog verification environments supporting multiple product generations.
• Develop verification plans using constrained-random verification, SVA, functional coverage, scoreboarding, and protocol checking.
• Drive verification closure through coverage analysis, debug methodologies, and metric-based execution.
• Partner with Architecture, RTL, Physical Design, Firmware, System Validation, and Silicon teams throughout the product lifecycle.
• Lead root-cause analysis of integration, timing, protocol, and performance issues and provide verification-driven architectural feedback.
• Mentor senior verification engineers and establish organization-wide verification best practices.
• Improve verification infrastructure, automation, CI/CD workflows, and regression efficiency.
• Support post-silicon bring-up, characterization, and system validation activities.

Requirements

Core technical and professional requirements. Degrees are summarized separately under Education Requirements.

Must-have:

• 15+ years of design verification experience on complex ASIC, SoC, or FPGA products.
• 10+ years verifying DDR memory subsystems, including controllers and PHY architectures.
• Strong expertise in SystemVerilog, UVM, SystemVerilog Assertions (SVA), constrained-random verification, and functional coverage.
• Deep knowledge of memory technologies: DDR4, DDR5, LPDDR4, LPDDR5, HBM/HBM2/HBM3.
• Experience with DDR PHY architectures, memory controller design, initialization/training sequences, and calibration algorithms.
• Familiarity with AXI/AMBA interconnects, cache coherency, and memory subsystem integration.
• Proven experience verifying high-performance memory interfaces in large SoC or FPGA environments.
• Strong debugging skills with industry simulators, waveform tools, protocol analyzers, and regression infrastructure.
• Excellent communication skills and ability to influence cross-functional technical direction.

Nice-to-have:

• Experience with additional high-speed interfaces (PCIe, Ethernet, CXL, UCIe, SerDes).
• Formal verification experience and use of emulation/FPGA prototyping platforms.
• Scripting skills (Python, Perl, Tcl, Shell) and experience implementing CI/CD for scalable regression frameworks.
• Track record of mentoring senior engineers and defining verification methodologies at scale.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline is required. A Master's or Ph.D. in EE, CE, or CS is preferred.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.