Principal Engineer - Design Verification

Job Title

Principal Engineer - Design Verification

Role Summary

Lead and own design verification (DV) for complex SoC platforms within the Data Centre Engineering — Compute & Storage organization. The role focuses on end-to-end DV planning, execution, automation, and sign-off across IP, subsystem, and SoC levels.

Work closely with design, silicon bring-up, firmware, and cross-functional teams to ensure correctness, performance, and timely delivery of verification milestones.

Experience Level

Senior; typically requires 12+ years of relevant design verification experience and demonstrated experience leading technical teams.

Responsibilities

Primary responsibilities include technical leadership of verification activities, architecture of testbenches, and delivery of verification sign-off.

• Lead end-to-end SoC DV planning, execution, and sign-off; define verification milestones and gate criteria.
• Define and improve DV processes, methodologies, and automation for efficient, high-quality execution.
• Create test plans, testbench architecture, and coordinate milestone reviews with IP, subsystem, and SoC teams.
• Architect, implement, and maintain UVM- and C-based simulation testbenches; develop BFMs, scoreboards, monitors, and verification components.
• Drive simulation, coverage closure, gate-level simulations, and debug simulation failures to identify root causes.
• Collaborate with silicon bring-up and firmware teams to support post-silicon validation and bring-up activities.
• Mentor and lead verification engineers and technical leads; provide technical guidance and code/review standards.

Requirements

Must-have skills and experience for successful execution of the role; listed concisely.

• Must-have: 12+ years of hands-on experience in SoC/subsystem/IP verification with demonstrated leadership of technical teams.
• Must-have: Proven experience verifying ARM-based SoCs, including familiarity with ARM boot sequences.
• Must-have: Strong knowledge of ARM architecture and AMBA bus standards (AXI-4, CHI, ACE).
• Must-have: Experience with industry-standard interfaces such as DDR, HBM, PCIe, Ethernet, and USB.
• Must-have: Expertise in UVM-based testbench development (SOC/subsystem/block level), including BFMs, scoreboards, and monitors.
• Must-have: Proficiency writing and debugging tests in UVM and C; strong simulation debug skills.
• Must-have: Familiarity with EDA verification tools (Cadence, Synopsys, Mentor, ARM tools) and assertion-based formal verification.
• Must-have: Scripting proficiency (Tcl, Perl) and experience with version control tools (CVS, SVN, Git).
• Must-have: Eligibility to access export-controlled technology as required by U.S. export control laws.
• Nice-to-have: Experience with hardware emulation, SystemC TLMs, and post-silicon bring-up/firmware integration.
• Nice-to-have: Prior work on high-performance data-processing/AI SoC platforms and CXL products.

Education Requirements

Master's or Bachelor's degree required (posting lists "Master's/Bachelor’s degree"); specific field of study not specified. The role also specifies 12+ years of relevant experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.