Principal Engineer, Design Verification Architecture

Job Title

Principal Engineer, Design Verification Architecture

Role Summary

Lead definition and architecture of verification strategies and methodologies for complex silicon designs. The role focuses on testbench architecture, UVM/formal verification approaches, test strategy definition, and integration of block-level verification into chip-level environments.

Work with architecture, design, analog and digital teams to drive functional and post-silicon validation, mentor technical staff, and influence technical direction. This position is a Position of Trust and requires an extended background investigation where permitted by local law.

Experience Level

Senior-level. Experience guidance from the posting: 12+ years with a Bachelors degree, 8+ years with a Masters degree, or 6+ years with a PhD. Equivalent practical experience may be acceptable per business needs.

Responsibilities

Main responsibilities include defining verification architecture, building testbenches, and ensuring integration and closure across verification activities.

• Define and document verification strategies, methodologies, and solutions for silicon designs.
• Architect and implement testbenches using UVM or formal-based approaches.
• Integrate block-level testbenches into chip-level UVM environments and verify integration.
• Develop test strategies, architectures, and detailed test plans to validate blocks against specifications.
• Collaborate with analog and digital teams to support post-silicon validation and debug.
• Create random test generation plans, run functional simulations, and identify/resolve specification gaps.
• Perform failure analysis and coverage analysis and drive closure of verification issues.
• Define and implement security validation strategies to improve coverage.
• Act as a technical leader and mentor, aligning technical vision with organizational goals.

Requirements

Must-have technical skills and experience. Preferred items are noted where applicable.

• Must-have: Proficiency in SystemVerilog and UVM-based verification methodologies.
• Must-have: Strong experience with validation protocols, IP/SoC integration, and hardware simulation/debugging/validation environments.
• Must-have: Solid understanding of RTL design and microarchitecture fundamentals.
• Must-have: Experience developing test plans, writing tests, and performing coverage and failure analysis.
• Must-have: Ability to architect testbenches and integrate verification environments at chip level.
• Nice-to-have: Experience developing security validation strategies and increasing security coverage.
• Nice-to-have: Demonstrated leadership in driving cross-functional initiatives and mentoring technical staff; strong communication and collaboration skills.

Education Requirements

Posting specifies a Bachelors/BS degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience. The posting also references Masters and PhD degrees in relation to reduced experience requirements (8+ years with a Masters, 6+ years with a PhD). Equivalent practical experience is explicitly allowed per business needs. No specific certifications were listed.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.