Principal Engineer, Design Verification
Marvell TechnologyJob Title
Principal Engineer, Design Verification
Role Summary
Senior verification engineer responsible for architecting and implementing UVM-based simulation testbenches and verification plans for custom data‑center silicon. Works within the Data Centre Engineering Group to verify IP and block-level logic, ensure performance and correctness, and drive coverage closure and gate‑level validation.
Experience Level
Senior level — expects substantial industry experience (guidance in posting: ~13+ years with a Bachelor's degree or ~11+ years with a Master’s degree).
Responsibilities
Primary responsibilities include planning, implementing, and validating verification strategies and collaborating with design teams to close coverage and debug issues.
- Architect and implement UVM simulation testbenches for IP and subsystem verification.
- Develop and execute detailed test plans to verify functional correctness and performance.
- Run simulations, own failures, perform root‑cause analysis and drive fixes through to closure.
- Coordinate with logic designers for test plan development, execution, coverage metrics, and gate‑level simulations.
- Analyze coverage results and lead activities to achieve verification closure.
Requirements
Must-have technical skills and experience; listed concisely. Nice-to-have items are separated.
- Must-have: Strong background in IP verification, including verification methodology and testbench development.
- Proficient in Verilog, SystemVerilog, UVM, and C/C++.
- Solid understanding of verification methodologies: object‑oriented techniques, white‑box/black‑box testing, directed and random testing, coverage analysis, and gate‑level simulation practices.
- Experience in Unix/Linux environments and basic scripting; Shell, Perl, or Python skills are useful.
- Strong analytical, debugging, communication, and teamwork skills; ability to manage multiple tasks in a fast‑paced environment.
- Experience working on processor‑based subsystems.
- Nice-to-have: Experience with hardware security (HW Security) and advanced scripting/automation for verification flows.
Education Requirements
Bachelor's degree in Computer Science or Electrical Engineering with ~13+ years of relevant experience, or Master's degree in Computer Science or Electrical Engineering with ~11+ years of relevant experience. No other certifications were specified.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
