Principal Engineer - Design (SoC Integration and RTL/IP)
MicrochipJob Title
Principal Engineer - Design (SoC Integration and RTL/IP)
Role Summary
Lead SoC integration, RTL/IP design, and FPGA prototyping for the dsPIC microcontroller product line. Drive top-level and subsystem integration, RTL development, IP design, and FPGA validation.
Work cross-functionally with architecture, verification, physical design, firmware, and system teams to deliver integrated, reusable hardware designs and post-silicon fixes.
Experience Level
Senior - requires 10+ years of experience in ASIC/SoC design, RTL development, FPGA work, or SoC integration.
Responsibilities
Primary duties include design, integration, verification support, and technical leadership for SoC projects.
- Perform top-level and subsystem integration of processors, memories, peripherals, and custom IPs.
- Integrate IPs using AMBA AXI/AHB/APB and proprietary bus interfaces; handle address mapping and pad/pin connectivity.
- Implement clock/reset integration, interrupt routing, and related architecture.
- Develop synthesizable RTL (SystemVerilog) for peripherals, controllers, wrappers, and power-management modules.
- Support synthesis, static timing analysis (STA), timing closure, and lint resolution; perform CDC/RDC analysis and fixes.
- Lead FPGA prototyping, synthesis/place-and-route support, constraint development, and FPGA-based validation.
- Drive post-silicon debug and ECO revisions; produce integration documentation and design quality reports.
- Lead design reviews, mentor junior engineers, and collaborate with cross-functional teams on IP/product decisions.
Requirements
Must-have technical skills and hands-on experience; preferred items listed separately.
- 10+ years of experience in ASIC/SoC design, RTL development, FPGA, or SoC integration.
- Strong knowledge of SystemVerilog.
- Experience with AMBA AXI/AHB/APB protocols and SoC integration (clock/reset architecture, memory mapping).
- Hands-on experience with Vivado or Quartus, synthesis, static timing analysis, and timing closure.
- Familiarity with simulators such as QuestaSim, VCS, or Xcelium.
- Practical experience resolving CDC/RDC issues, RTL lint, and timing/synthesis problems.
- Python and Tcl scripting for design flows and tool automation.
- Proven ability to lead technical reviews and mentor engineering teams.
Nice-to-have:
- Experience with ARM or RISC-V SoCs and common interfaces (Ethernet, USB, SPI, I2C, UART).
- Knowledge of low-power design, DFT integration, formal verification, and FPGA place-and-route/timing closure.
- Experience with FPGA-based validation and constraint development.
Education Requirements
Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field is stated as required; a Master's degree in a related field is listed as preferred.
About the Company
Company: Microchip
Headquarters: Chandler, Arizona, USA
Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.
