Principal Engineer - Design (FPGA)

Job Title

Principal Engineer - Design (FPGA)

Role Summary

Senior FPGA design engineer responsible for FPGA-based platform development, system integration, and validation to support USB and Ethernet PHY IP and SoC products. Works closely with digital, analog, firmware, software, verification, and validation teams to deliver production-ready hardware and FPGA images.

Experience Level

Senior — requires 10+ years of FPGA and/or digital design experience.

Responsibilities

Deliver FPGA solutions and support system-level bring-up and validation.

• Design, implement, and optimize synthesizable RTL for FPGA (Verilog/SystemVerilog).
• Develop self-checking testbenches and perform functional simulation and debug.
• Perform synthesis, implementation, timing analysis, and place-and-route using vendor tools.
• Integrate FPGA platforms with mixed-signal IP and SoC components; participate in board-level bring-up and hardware debug.
• Define timing constraints and design multi-clock-domain systems.
• Collaborate across hardware, firmware, software, ASIC, analog, verification, and validation teams during integration and lab testing.
• Produce clear design documentation: requirements, architecture, block diagrams, and interface control documents.
• Use scripting and automation to support build, simulation, synthesis, and implementation flows.

Requirements

Must-have technical skills, tools, and work conditions.

• 10+ years of experience in FPGA and/or digital design with hands-on RTL coding, simulation, synthesis, and hardware implementation.
• Proficiency in Verilog and/or SystemVerilog for synthesizable RTL.
• Experience creating self-checking testbenches and using QuestaSim/ModelSim or equivalent.
• Experience with FPGA synthesis, implementation, timing analysis, and place-and-route using AMD/Xilinx Vivado or equivalent.
• Ability to define and analyze timing constraints and design systems with multiple clock domains.
• Experience with FPGA system integration and board-level bring-up; loading FPGA images and debugging on physical boards.
• Hands-on use of lab debug equipment: oscilloscopes, logic analyzers, protocol analyzers, and embedded logic-debug tools.
• Proficiency in scripting (Tcl, Python, Perl, Linux shell) and familiarity with C++ or Rust for automation tasks.
• Experience with revision-control systems such as Perforce, Git, DesignSync, including tagging/branching and configuration management.
• Strong verbal and written communication skills and ability to participate in technical discussions and reviews.
• Located in the Chandler Design Center (on-site requirement).
• Willingness to travel up to 25%.
• Nice-to-have: experience with USB and Ethernet PHY architectures and protocols.

Education Requirements

Not specified.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.