Principal Engineer - Design

Job Title

Principal Engineer - Design

Role Summary

Lead digital design, DFT, physical implementation, and static timing analysis for high‑speed optical networking integrated circuits within the Communications Business Unit.

Drive RTL‑to‑netlist flows and STA signoff across macros, subsystems and full‑chip designs while collaborating with RTL, DFT and APR teams on advanced process nodes.

Experience Level

Senior — targeted at experienced engineers (approximately 10+ years) with proven expertise in synthesis, STA and formal verification.

Responsibilities

Primary responsibilities include technical leadership for timing, synthesis and implementation across macro and chip levels, and ensuring quality of deliverables.

• Develop macro constraints (synthesis, STA, and layout), RAM generators, and flow configurations for high‑speed complex macros and subsystems.
• Perform STA signoff across design hierarchy for multiple modes and multiple corners (MMMC).
• Define and maintain RTL synthesis flows and methodologies; drive quality and QOR improvements.
• Collaborate with RTL, DFT, and APR teams to ensure correct constraints, floorplanning, macro placement, and deliverables.
• Validate pre/post netlist quality using CLP, LEC, and in‑house checks; troubleshoot timing and synthesis issues.
• Own RTL‑to‑pre‑layout netlist generation and STA signoff for macros, subsystems, and full‑chip designs.
• Mentor peers and influence design methodologies to meet tapeout requirements.
• Coordinate across teams during tapeout and production release activities.

Requirements

Must-have technical skills and experience; nice-to-have items noted separately.

• Must have: Approximately 10 years experience in synthesis, STA and formal verification using mainstream tools.
• Must have: Hands-on RTL design and synthesis; low‑power logic insertion using UPF/CPF and STA signoff at macro and SoC level.
• Must have: Tapeout experience on one or more projects at 16nm or smaller process technologies.
• Must have: Proficiency with synthesis tools such as Cadence Genus or Synopsys DC/FC.
• Must have: Strong scripting/coding skills (TCL, Perl or Python) and excellent analytical/debugging ability.
• Must have: Good understanding of timing models, DFT, libraries, and hierarchical budgeting flows.
• Nice to have: Formal verification beyond basic flows and prior APR collaboration experience.
• Other: Good verbal and written English communication and interpersonal skills; travel up to 25%.

Education Requirements

Bachelor's or graduate degree in Computer Science, Electrical/Electronics or VLSI Engineering.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.