Principal Engineer - CAD (Physical Verification)

Job Title

Principal Engineer - CAD (Physical Verification)

Role Summary

Member of the CAD group responsible for developing and supporting back-end physical verification flows and rule decks across multiple process technologies. The role focuses on automation, verification deck development, debugging verification failures, and collaborating with technology and device engineering to improve manufacturability and yield.

Experience Level

Senior-level engineer. The posting requests approximately 10+ years of experience in developing and supporting physical verification activities.

Responsibilities

Primary technical responsibilities and typical assignments include:

• Develop physical verification regression test cases to QA verification decks and PDKs.
• Support layout and design engineers with DRC/LVS/PERC activities using tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules.
• Create, verify, and enhance rule decks and PERC setups for multiple foundries and process nodes (4nm to 600nm).
• Apply advanced EDA methods for ESD, ERC, Voltage-Aware DRC, via-doubling, and other DFM checks.
• Collaborate with Technology Development and Device Engineering to add devices, develop DRC rules, and implement design-for-manufacturability checks.
• Debug physical verification issues using visualizers (RVE, Vue, etc.) and improve verification flows for quality and reliability.
• Provide remote support to global sites and maintain regression infrastructure for multiple PDKs.

Requirements

Key skills and experience required or strongly preferred.

• 10+ years of experience developing and supporting physical verification activities for semiconductor designs.
• Strong, hands-on experience with Siemens Calibre and/or Cadence Pegasus verification tools, including PERC setup.
• In-depth knowledge of Calibre DesignRev scripting and familiarity with Calibre Interactive and CalibreDRV.
• Fluent with SVRF and TVF rule languages; experienced with Calibre/Pegasus/Hercules syntax and semantics.
• Proven ability to debug PV issues using RVE, Vue, or other EDA visualizers.
• Solid programming and automation skills (Tcl/Tk, Perl, Python, and other scripting languages) for tool integration and flow automation.
• Strong understanding of layout rules, device identification, foundry rule interpretation, and DFM practices that affect quality, reliability, and yield.
• Experience supporting multiple foundries and PDKs (TSMC, GlobalFoundries, Vanguard, Dongbu, Magnachip, etc.) is desirable.
• Excellent verbal and written communication and interpersonal skills.
• Nice-to-have: extraction, reliability, and dynamic noise analysis experience.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field is specified (the posting requests this along with 10 years of experience). A Master’s in Electrical Engineering or related field is listed as preferred.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.