Principal Engineer - CAD (Physical Verification)

Job Title

Principal Engineer - CAD (Physical Verification)

Role Summary

Work in Microchip's CAD group developing and supporting physical verification flows for back-end chip design across multiple process nodes and foundries. The role focuses on creating and maintaining verification run decks, automation, debugging verification failures, and collaborating with layout, design, technology, and device engineering teams.

Experience Level

Senior — typically 10+ years of experience in physical verification, CAD flow development, or related EDA engineering.

Responsibilities

Primary responsibilities cover verification flow development, tool support, and cross-team collaboration.

• Develop and maintain physical verification regression test cases and run decks (DRC/LVS/PERC).
• Support layout and design engineers in physical verification using Siemens Calibre, Cadence Pegasus, or similar tools.
• Debug verification failures using visualizers such as RVE or Vue and refine decks accordingly.
• Automate verification procedures and integrate PERC/other advanced checks into flows.
• Work with Technology Development and Device Engineering to implement DRC rules, device identification, and DFM checks.
• Verify and enhance foundry rule decks and support multiple PDKs across technology nodes.
• Provide remote support to global sites for layout verification and issue resolution.
• Contribute to improving flow quality, reliability, and yield through tooling and process enhancements.

Requirements

Must-have technical skills and experience for immediate contribution.

• Extensive hands-on experience with Siemens Calibre and/or Cadence Pegasus for DRC, LVS, and PERC.
• Proficient in Calibre DesignRev scripting and familiar with SVRF and TVF.
• Skilled at debugging PV issues using RVE, Vue, or other EDA visualizers.
• Experience customizing interactive tool behavior (e.g., Calibre Interactive) and integrating tools into flows.
• Programming/scripting skills: Tcl/Tk, Perl, Python; ability to script inside and outside EDA tools.
• Strong knowledge of layout rules, device identification, foundry rules, and DFM practices affecting yield and reliability.
• Familiarity with Cadence Virtuoso and/or CalibreDRV.
• Experience supporting multiple PDKs and nodes; able to set up PERC where required.

Nice-to-have:

• Experience with Synopsys Hercules or similar verification tools.
• Extraction, reliability, or dynamic noise analysis experience.
• Background supporting a broad range of foundries (TSMC, GlobalFoundries, Vanguard, Dongbu, Magnachip, etc.) and nodes from advanced to mature processes.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field (stated requirement). Master's degree in Electrical Engineering or related field is preferred. The posting indicates ~10 years of experience expectation alongside the Bachelor's degree requirement.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.