Principal Engineer, ASIC/VLSI Synthesis and Design

Job Title

Principal Engineer, ASIC/VLSI Synthesis and Design

Role Summary

Senior-level synthesis and front-end implementation engineer responsible for timing-constraint development, logic synthesis, equivalency checking, STA, and front-end flows for SoC and block-level designs. The role supports high-speed, advanced-node silicon (e.g., TSMC N4/N5) and collaborates with architecture, RTL, DFT, analog, and physical design teams to achieve timing, power, and area goals.

Experience Level

Senior. Typical experience: ~10+ years for candidates with a Bachelor’s degree; ~5+ years with a Master’s or PhD. Minimum stated industry experience: 5+ years in ASIC implementation and synthesis.

Responsibilities

Primary responsibilities include front-end implementation, timing, and synthesis tasks for complex SoC designs.

• Develop and validate timing constraints for complex hierarchical SoC and block designs.
• Collaborate with Architecture, RTL, DFT, and Analog teams to define consolidated timing modes and sign-off flows.
• Own synthesis, UPF development, logical equivalence checks (LEC), functional ECOs, and related front-end flows.
• Perform physical-aware synthesis and work with industry-standard tools to meet timing and power targets.
• Analyze power/performance/area trade-offs and incorporate optimizations into implementation flows.
• Investigate and resolve EDA tool issues, working independently or with tool vendors.
• Automate front-end flows using scripting (e.g., Tcl, Python) and maintain delivery checklists for netlist handoffs.
• Document best practices and lessons learned to improve future projects.

Requirements

Must-have technical skills, tools experience, and behaviors; nice-to-have items noted where applicable.

• Must-have: Minimum 5+ years industry experience in ASIC implementation and synthesis; strong understanding of RTL-to-GDSII flows, synthesis and STA methodologies, timing constraint development, and timing closure techniques.
• Must-have: Hands-on experience with synthesis and STA tools and scripting for automation (Tcl, Python; Perl experience noted in source).
• Must-have: Experience performing functional ECOs and LEC using industry-standard flows.
• Must-have: UPF development and UPF validation experience for blocks and SoCs.
• Must-have: Familiarity with physical design and timing optimization strategies to achieve closure on high-speed designs.
• Nice-to-have: Experience with Fusion Compiler, Conformal ECO, Conformal Low Power (CLP), and deep technology nodes (5nm/4nm).
• Proven track record delivering designs that meet performance, power, and area goals; strong problem-solving and cross-functional communication skills.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field (with ~10–15 years relevant experience) OR Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields (with ~5–10 years relevant experience). The posting presents degree plus experience combinations as the expectation; equivalent practical experience is considered as part of the stated experience ranges.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.