Principal Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis

Job Title

Principal Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis

Role Summary

Responsible for STA signoff, timing constraint development, ECOs, and timing closure for complex SoC and block-level designs in advanced process nodes. Work within a cross-functional team supporting Marvell's Photonic Fabric and high-speed interconnect silicon.

Focus areas include static timing analysis, flow automation, timing quality-of-results, and improving signoff methodologies.

Experience Level

Senior-level. Typical experience: Bachelor's +10–15 years, or Master's/PhD +5–10 years; minimum 5 years industry ASIC timing/STA experience.

Responsibilities

Key responsibilities include:

• Develop and validate timing constraints and consolidated timing modes for SoCs and blocks.
• Run STA signoff flows and perform post-route timing checks and quality-of-results analysis.
• Create and execute timing ECOs and timing budgeting to achieve closure.
• Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
• Automate STA flows, reporting, and dashboards using scripting (Tcl, Python, etc.).
• Generate QoR dashboards, histograms, and metrics across all timing modes.
• Coordinate with architecture, RTL, DFT, and analog teams to resolve timing issues and consolidate constraints.
• Investigate and resolve EDA tool issues and collaborate with tool vendors when necessary.
• Document best practices and lessons learned to improve future projects.

Requirements

Must-have skills and experience:

• Minimum 5 years industry experience in ASIC timing and static timing analysis with demonstrated signoff experience.
• Strong understanding of ASIC design flows from RTL to GDSII and timing constraint development for hierarchical designs.
• Proficiency with STA tools (e.g., Synopsys PrimeTime) and timing signoff methodologies.
• Scripting experience for automation and reporting (Tcl, Python; Perl acceptable).
• Experience creating timing ECOs and applying timing optimization strategies to achieve deterministic closure.
• Familiarity with physical design and timing optimization techniques.
• Experience with advanced process nodes preferred (e.g., TSMC N4/N5).
• Strong problem-solving skills, attention to detail, and effective cross-functional communication.

Nice-to-have:

• Experience with power analysis and logical equivalence checking (LEC) workflows.
• Experience with high-bandwidth or photonic interconnect designs.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 10–15 years of relevant experience; or a Master’s degree or PhD in Computer Science, Electrical Engineering, or related field with 5–10 years of relevant experience. The posting also specifies a minimum of 5 years of industry experience in ASIC timing/STA.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.