Principal, Emulation Engineer

Job Title

Principal, Emulation Engineer

Role Summary

Join the Pre-Silicon Emulation team within the Connectivity Business Unit to develop and run emulation models and tests for connectivity SoC programs (Optical DSPs, PCIe/CXL retimers, high-speed Ethernet PHYs, AEC/AOC devices). The team enables early firmware bring-up, hardware/software co-validation, and system-level debug on platforms such as Palladium, Veloce, and Zebu.

Work closely with design, verification, firmware, software, and post-silicon teams to reduce risk and accelerate time-to-silicon.

Experience Level

Senior level. Typically requires 7+ years of relevant experience; candidates with a Master's or PhD may be considered with ~3+ years of relevant experience.

Responsibilities

Primary responsibilities include model bring-up, test development, and system-level debug on emulation platforms.

• Execute emulation model bring-up, test development, and debug for connectivity silicon programs on Palladium, Veloce, and Zebu.
• Implement platform configurations, transactors, speed bridges, protocol adapters, and supporting firmware/software stacks.
• Collaborate with design, validation, firmware, and post-silicon teams to identify and resolve emulation bottlenecks and improve validation coverage.
• Work with EDA and emulation hardware vendors to resolve tooling and platform issues.
• Develop and maintain HW/SW enablement flows, scripts, and automation to improve emulation usability, productivity, reliability, and utilization.

Requirements

Must-have technical skills and experience:

• Hands-on experience with SoC emulation platforms such as Palladium, Veloce, or Zebu, including building and maintaining emulation models for SoC designs.
• Experience with simulation and debug in Verilog/SystemVerilog environments and emulation-based debug workflows.
• Familiarity with SoC development flows and system-level validation.
• Scripting and automation skills (Python, Perl, Tcl, and/or UNIX shell).
• Proven ability to collaborate effectively with cross-functional teams and external vendors.

Nice-to-have:

• Experience emulating networking devices or mixed-signal designs, including PHY or Layer-2/Layer-3 functionality.
• Exposure to connectivity-focused silicon such as Optical DSPs, PCIe/CXL retimers, high-speed Ethernet PHYs, or AEC/AOC enablement devices.
• Experience improving emulation infrastructure or enabling firmware/software bring-up via emulation.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 7+ years of relevant experience; or a Master's/PhD with 3+ years of relevant experience. No specific certifications are required; export-control eligibility may be required for access to certain technologies.

Reasonable accommodation requests during the selection process can be directed to Marvell HR Helpdesk at TAOps@marvell.com.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.