Principal EDA Engineer

Job Title

Principal EDA Engineer

Role Summary

Technical authority for Calibre-based physical verification and signoff for advanced analog and mixed-signal programs. Lead development and optimization of Calibre verification flows, rule decks, and supporting tools; provide tapeout readiness and high-impact issue resolution across multiple projects and process nodes.

Experience Level

Senior / Principal level. Expectation: typically 10+ years of relevant EDA or physical verification experience.

Responsibilities

Primary responsibilities include technical leadership of verification flows, rule development, and tapeout support:

• Serve as Calibre technical authority across DRC, LVS, ERC, PERC, extraction, and signoff methodology.
• Define, develop, maintain, and optimize Calibre verification flows and infrastructure for analog/mixed-signal teams.
• Write, debug, and enhance SVRF and TVF rule sets and supporting scripts or code.
• Lead tapeout readiness: final signoff checks, waiver management, antenna issue resolution, and deliverable preparation.
• Integrate, validate, and version foundry rule files and process updates for advanced-node programs.
• Resolve complex verification, runset, extraction, and rule-deck problems that impact schedules.
• Enable new projects by setting up verification environments and identifying early signoff risks.
• Develop automation, reporting, dashboards, and tools to improve debug efficiency, runtime, and resource use.
• Provide documentation, training, and mentorship to engineers on verification flows and signoff practices.

Requirements

Must-have technical skills and experience (concise):

• Expert-level proficiency with Mentor Calibre across DRC, LVS, ERC, PERC, parasitic extraction, and signoff flows.
• Hands-on experience writing, debugging, and maintaining SVRF and TVF rule sets.
• Strong experience building scripts, tools, and automation to extend Calibre workflows and support debugging and analysis.
• Proven tapeout and signoff support experience, including waiver management and foundry-facing requirements.
• Advanced-node experience with TSMC design rules and verification challenges (examples: 16nm, 5nm, 4nm).
• Proven ability to lead resolution of complex backend verification and extraction issues.
• Familiarity with Linux-based EDA environments, compute infrastructure, license usage, and version-controlled design data workflows.
• Ability to work effectively with analog layout, design, CAD, and project teams in a multi-project environment.
• Strong understanding of analog layout practices and physical verification signoff expectations.
• Nice-to-have: Perforce experience, Cadence Virtuoso customization (SKILL), GUI/reporting/dashboard development, EDA license/compute optimization, AI-assisted verification methods.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related field, or an equivalent combination of education and 10+ years of related experience.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.