Principal Digital Engineer (DFT Design)

Job Title

Principal Digital Engineer (DFT Design)

Role Summary

Join the Power Management IC team to lead digital DFT (design-for-test) activities for automotive PMIC products. You will design and validate test logic and patterns, insert LogicBIST, and work across digital design, physical implementation, test engineering and silicon validation to meet automotive test and safety targets.

This role supports automotive ASIL test requirements and focuses on delivering high-quality, manufacturable DFT solutions for production silicon.

Experience Level

Senior / Principal-level engineer. Typical experience: 12+ years in digital design and DFT (role expects extensive prior tapeout and production-validation experience).

Responsibilities

Primary responsibilities include design, verification, and delivery of DFT features and test patterns, and cross-team integration to support production validation.

• Insert DFT/scan on digital logic and perform ATPG; validate test patterns on pre- and post-layout gate-level netlists.
• Deliver and validate test patterns with Test Engineering; debug failures on ATE and update patterns accordingly.
• Insert and verify LogicBIST using industry-standard tools; optimize LBIST during synthesis or RTL flow.
• Improve scan coverage and modify RTL to achieve required coverage while reducing ATE test time.
• Participate across the digital flow: micro-architecture, partitioning, RTL (Verilog/SystemVerilog), timing constraints, synthesis, P&R interaction, timing analysis, LINT, CDC checks.
• Create top-level test-benches and run gate-level simulations for scan validation.
• Write and review DFT specifications and design documentation; organize and participate in design reviews and completion of checklists.
• Collaborate with architects, design, P&R, test and silicon validation teams to meet delivery and quality targets.
• Work on-site at the Chandler office at least three days per week.

Requirements

Must-have technical skills and experience; desirable items are listed separately.

• Extensive hands-on experience with scan insertion, ATPG, improving scan coverage, and LogicBIST insertion during synthesis or RTL flow.
• Experience performing gate-level simulations with test patterns and delivering patterns for silicon validation.
• Strong RTL coding fundamentals and synthesis exposure; solid understanding of synthesizable design, timing constraints and exceptions.
• Hands-on experience with industry tools from Synopsys, Cadence, Mentor, or Siemens for scan, LBIST and ATPG; Tetramax is a strong advantage.
• Track record of multiple tapeouts (hands-on DFT/Scan on at least several production projects; posting cites 8+ tapeouts as typical).
• Attention to detail, analytical problem-solving, and strong written and verbal cross-functional communication skills.
• Ability to propose and implement process improvements and new flows across teams.
• Nice-to-have: mixed-signal experience; exposure to automotive test requirements and ASIL processes.

Education Requirements

BSEE required; MSEE preferred. The role typically expects senior experience levels (the posting references an expectation of roughly Master+12 years or Bachelor+15 years of relevant digital design and DFT experience).

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.