Principal Digital Engineer

Job Title

Principal Digital Engineer

Role Summary

Front-end ASIC design engineer responsible for architecture, RTL design, and functional verification of full-custom digital and mixed-signal superconducting circuits. Work closely with synthesis, place-and-route, and verification teams to deliver manufacturable ASIC designs.

Position requires collaboration across teams, occasional travel (~10%), and support for production test/vector generation and digital design automation.

Experience Level

Senior level. Typical qualification examples: Bachelor's + 5 years, Master's + 3 years, or Ph.D. + 1 year of relevant experience (or equivalent experience).

Responsibilities

Key responsibilities include design, verification, and handoff tasks for digital ASICs.

• Write RTL (Verilog, SystemVerilog, or VHDL) and develop functional testbenches.
• Create functional verification plans from circuit requirements and execute verification.
• Perform synthesis, formal verification, and static timing analysis using industry tools.
• Generate manufacturing test vectors and manufacturing test plans.
• Estimate power for superconducting circuits and advise on power-related tradeoffs.
• Coordinate with place-and-route engineers on floorplanning, clock tree constraints, and timing closure.
• Develop or improve automated procedures to streamline digital design workflows.

Requirements

Must-have technical skills, clearance and eligibility, plus relevant tool experience. Preferred items follow.

• Must-have: Proficiency in RTL coding (Verilog/SystemVerilog/VHDL), writing testbenches, and synchronous digital design concepts.
• Must-have: Experience across the front-end ASIC flow (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion).
• Must-have: Experience with ASIC simulation and synthesis tools (examples: Mentor ModelSim, Cadence Xcelium/Incisive, Synopsys VCS; Synopsys Design Compiler, Cadence Genus/RTL Compiler; Synopsys PrimeTime or Cadence Tempus).
• Must-have: Ability to generate manufacturing test vectors and test plans.
• Must-have: U.S. Citizenship and ability to obtain/maintain a U.S. Government Secret Clearance.
• Nice-to-have: Knowledge of superconductivity principles and superconducting circuit design.
• Nice-to-have: Experience with chip-level integration, ASIC chip lead responsibilities, CAD network/tool configuration, and data management.
• Nice-to-have: Familiarity with custom layout (Cadence Virtuoso), physical verification (LVS/DRC) using Assura or Calibre, scan insertion/ATPG, and power estimation techniques.

Education Requirements

Bachelor's degree in Science, Technology, Engineering, Mathematics (STEM) or related technical field with 5 years' experience; Master's with 3 years; Ph.D. with 1 year. An additional 4 years of relevant experience may be considered in lieu of a degree.

About the Company

Company: Northrop Grumman

Headquarters: Falls Church, Virginia, United States

Northrop Grumman is a leading global aerospace and defense technology company that provides innovative solutions in mission systems, electronics, and software. With a legacy of significant advancements in technology, we empower employees to tackle complex challenges and create revolutionary systems that enhance global security. Our diverse teams focus on engineering innovation and product development, delivering solutions that support military and civilian customers worldwide.