Principal Digital Design Engineer

Job Title

Principal Digital Design Engineer

Role Summary

The Principal Digital Design Engineer will lead a digital IP team that develops, curates, and delivers reusable digital IP blocks and infrastructure to internal product teams. The role combines technical leadership, hands-on RTL design, IP packaging, evaluation of third-party IP, and process/flow improvements to accelerate ASIC/SoC development.

Experience Level

Senior-level. The posting specifies 15+ years of relevant experience.

Responsibilities

Accountable for technical leadership, IP delivery, and design-quality processes for digital IP used across multiple business units.

• Provide technical leadership and mentorship to a team of digital design engineers.
• Architect and implement key digital blocks (accelerators, datapaths) in Verilog/SystemVerilog with configurable PPA tradeoffs.
• Drive design reviews, establish and enforce quality metrics, and manage schedules and deliverables with stakeholders.
• Package IP for integration (RTL, constraints, CDC waivers, DFT artefacts, software sequences) and maintain an IP catalog.
• Define and run evaluation flows and benchmarks for home-grown and 3rd-party IP (PPA, DV robustness, DFT, integration effort).
• Lead consolidation and curation of standard peripherals, processor cores, and interface IP; simplify team processes and remove ambiguity.
• Drive development of design-management and IP-centric infrastructure and workflows (source control, IP cataloging, etc.).
• Engage with internal customers to collect requirements, communicate status, and escalate risks.

Requirements

Must-have technical skills, experience, and behaviors for successful performance.

• 15+ years of relevant experience in digital design, architecture, or RTL implementation.
• Hands-on RTL coding experience in Verilog and SystemVerilog.
• Deep understanding of ASIC/SoC development lifecycle, including DV, timing constraints and closure, and physical implementation; hands-on experience in several of these areas.
• Proven experience leading large, complex hardware projects in a technical lead role.
• Experience specifying DV requirements (test plans, coverage metrics) and assessing DV quality.
• Strong knowledge of linting, CDC, formal equivalence, DFT concepts, power analysis, and low-power design techniques.
• Experience developing timing constraints, synthesis, and static timing analysis workflows.
• Familiarity with standard on-chip interfaces and protocols (APB/AHB/AXI/stream) and high-speed interfaces (DDR, PCIe, Ethernet, MIPI, HDMI, etc.).
• Excellent interpersonal and communication skills; ability to drive cross-functional discussions across geographically distributed teams.
• Willingness to travel approximately 10% of the time.
• Nice-to-have: experience with IP management and tools (Methodics, Perforce, GitHub), IP catalog creation, and experience evaluating/packaging third-party IP.

Education Requirements

Minimum B.E. / B.Tech degree in Electrical, Electronics, or Computer Science.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.