Principal Digital Design Engineer / Chip Lead

Job Title

Principal Digital Design Engineer / Chip Lead

Role Summary

Technical lead for a small senior digital team executing silicon validation and integration of high-speed interface (PHY-adjacent) solutions from architecture to tape-out. The role spans RTL design, timing closure, synthesis, verification coordination, IP integration, and tape-out sign-off.

Experience Level

Senior — role expects significant experience; posting requests 10+ years of ASIC/digital design experience and prior tape-out in a lead or senior designer role.

Responsibilities

Primary responsibilities include chip-level architecture and delivery leadership across digital and mixed-signal interfaces.

• Define top-level chip architecture, partitioning between hard macros and soft IP and owning integration.
• Author, review, and maintain synthesizable SystemVerilog RTL for control blocks, CSRs, clocking control, and top-level integration.
• Develop and own chip-level timing constraints (SDC), CDC strategy, and block timing budgets for physical design.
• Drive logic synthesis and optimization (DC/Genus) to meet PPA targets.
• Coordinate verification strategy with DV: assertions, coverage-driven verification, formal methods, and constrained-random tests.
• Manage IP interfaces, vendor coordination, and integration agreements for hard and soft IP.
• Own tape-out checklist and sign-off coordination across teams to ensure clean foundry handoff.
• Produce architecture specs, block-level designs, and interface control documents; capture decisions and lessons for follow-on work.

Requirements

Must-have technical skills and experience for immediate contribution as a chip lead.

• 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or senior designer role.
• Expert-level SystemVerilog RTL design and coding best practices.
• Experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus).
• Proficiency with RTL simulation and debug tools (VCS, Xcelium or equivalent; Verdi/DVE for waveform debug).
• Practical CDC analysis experience and familiarity with CDC tools (SpyGlass, JasperGold CDC, or equivalent).
• Demonstrated experience integrating hard and soft IP blocks in mixed-signal or PHY-adjacent designs.
• Proven ability to lead a small technical team, make decisions with incomplete information, and own outcomes.
• Strong written communication skills for specifications and design documentation.
• Experience partnering with design verification teams to define verification plans, review coverage, and drive closure of functional and corner cases prior to tape-out.
• Proficiency in leveraging AI tools for productivity.

Preferred:

• Experience with high-speed PHY architectures (SerDes, DDR, or equivalent analog I/O).
• Familiarity with I2C management bus, Eye Monitor control logic, or PRBS-based error counting.
• Experience defining DFT strategies including scan insertion, ATPG planning, and boundary scan for high-speed I/O.
• Familiarity with OTP/fuse-based trim and calibration for PHY analog parameters.
• Prior experience in small-team or startup-like environments where roles are broad and flexible.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.