Principal Digital Design Engineer / Chip Lead

Job Title

Principal Digital Design Engineer / Chip Lead

Role Summary

Lead a small senior team to take high-speed interface innovations from architecture through tape-out. The role focuses on digital/RTL design, chip-level integration, timing closure, and coordination with analog, physical design, verification, and external IP vendors.

The team operates on a 3–5 year technology horizon to validate novel PHY solutions in silicon; the chip lead will provide technical ownership and drive execution.

Experience Level

Senior — requires 10+ years of ASIC/digital design experience with prior tape-out experience in a chip lead, design lead, or senior designer role.

Responsibilities

Main responsibilities include architecture, RTL, synthesis, timing, verification coordination, IP integration, and tape-out ownership.

• Define top-level chip architecture and partitioning between hard macros and soft IP.
• Author, review, and maintain synthesizable SystemVerilog RTL for control blocks, CSR/register files, clocking control logic, and top-level integration.
• Develop and own chip-level timing constraints (SDC), clock domain crossing strategy, and timing budgets per block.
• Drive logic synthesis and optimization (Design Compiler / Genus) to meet PPA targets.
• Coordinate verification strategy with DV: assertion-based, coverage-driven, formal methods, and constrained-random techniques.
• Manage IP interfaces and vendor coordination for hard macro and third-party soft IP integration.
• Own tape-out sign-off and handoff processes, coordinating across physical design, verification, and analog teams.
• Produce architecture specifications, block-level design documents, and interface control documents.
• Capture design decisions and lessons learned to inform follow-on roadmap and future chips.

Requirements

Must-have

• 10+ years of ASIC/digital design experience with at least one prior tape-out as a chip lead, design lead, or senior designer.
• Expert-level SystemVerilog RTL design and coding best practices.
• Strong experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus).
• Proficiency with RTL simulation and debug tools (VCS, Xcelium or equivalent; Verdi/DVE for waveform debug).
• Solid understanding of CDC analysis methodologies and tools (SpyGlass, JasperGold CDC, or equivalent).
• Proven experience integrating hard and soft IP in mixed-signal or PHY-adjacent environments.
• Demonstrated ability to lead technically on a small team, make decisions with incomplete information, and own outcomes.
• Strong written communication skills for producing specifications and technical documents.
• Experience partnering with design verification teams to define verification plans, review coverage metrics, and close functional and corner cases before tape-out.
• Proficiency in leveraging AI tools to improve engineering productivity.

Nice-to-have

• Experience with high-speed PHY architectures (SerDes, DDR, or equivalent analog I/O).
• Familiarity with I2C management bus, Eye Monitor control logic, or PRBS-based error counting.
• Experience defining DFT strategy including scan insertion, ATPG planning, and boundary scan for high-speed I/O.
• Familiarity with OTP/fuse-based trim and calibration architectures for PHY analog parameters.
• Prior experience in small teams or startup-like environments.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field (explicitly stated). No alternative "equivalent experience" language was provided in the posting.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.