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Principal Digital Design Engineer

NXP Semiconductors
May 07, 2026
Full-time
On-site
Catania, Sicily, Italy
RTL Design Jobs, Level - Senior

Job Title

Principal Digital Design Engineer

Role Summary

Lead the digital IC design activities for complex microcontroller System-on-Chip (SoC) products in NXP's Catania team focused on AI-at-the-edge MCUs. The role owns the end-to-end digital design flow and collaborates with analog, mixed-signal, verification, physical design and software teams to deliver high-performance, low-power products.

Work in a cross-functional team to define architecture, implement RTL, ensure integration and drive post-silicon validation and debug.

Experience Level

Senior β€” minimum 10+ years of experience in digital IC design, with proven leadership on complex SoC projects.

Responsibilities

Key responsibilities include leading digital design, verification and integration activities across the product lifecycle.

  • Lead the full digital IC design flow: specification, architecture, RTL (Verilog/SystemVerilog), synthesis, static timing analysis, formal verification, and power analysis.
  • Contribute to design-for-test (DFT) implementation and verification.
  • Collaborate with analog, mixed-signal and software teams to define interfaces and optimize system-level performance.
  • Develop digital architectures and design methodologies to meet performance, power and area targets.
  • Perform design verification using simulation, formal methods and hardware emulation.
  • Participate in post-silicon validation and debug to identify and resolve issues.
  • Mentor junior engineers and provide technical guidance to improve design processes.
  • Produce and maintain design documentation, specifications and test plans.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

  • Expertise in Verilog/SystemVerilog for RTL design and verification.
  • Proven experience with industry EDA tools for synthesis, STA, formal verification and simulation (examples: Synopsys Design Compiler/Primetime, Cadence Genus, Synopsys Formality, VCS, QuestaSim).
  • Strong understanding of digital design principles, clock domain crossing (CDC) issues, power integrity and low-power design techniques.
  • Experience with scripting languages for automation (Python, Perl, Tcl).
  • Familiarity with mixed-signal integration challenges and verification methodologies.
  • Excellent analytical, debugging, communication and collaboration skills; ability to lead technical discussions.

Nice-to-have: specific MCU or consumer SoC experience, hardware emulation leadership, extensive post-silicon debug ownership.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical field.


About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.

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Date Posted: 2026-05-07