Principal Digital Design Engineer

Job Title

Principal Digital Design Engineer

Role Summary

Design, develop and optimize digital logic for ASIC/FPGA products across the full design cycle: specification, RTL implementation, verification, synthesis, timing closure and silicon validation. Work closely with verification, physical design, firmware and system teams to deliver tape-outs that meet power, performance and area targets.

Experience Level

Senior-level — typically requires 10+ years of experience in digital design or ASIC/FPGA development with a proven record of tape-outs or product deliveries.

Responsibilities

Key day-to-day responsibilities include designing RTL, verifying functionality, optimizing implementation and supporting silicon bring-up.

• Write and review RTL using Verilog / SystemVerilog / VHDL; implement complex digital blocks and subsystems.
• Develop and execute functional verification, simulation-based testbenches and validation plans.
• Perform logic synthesis, static timing analysis, area and power optimization.
• Debug and troubleshoot issues at RTL, gate and silicon levels; support post-silicon bring-up and validation.
• Collaborate with verification, physical design, firmware and system teams to meet PPA targets.
• Participate in design reviews, code reviews and technical discussions.
• Use EDA tools for implementation and validation and maintain design documentation and release artifacts.
• Address clock domain crossing, pipelining, FSM design and CDC mitigation in designs.
• Ensure designs comply with bus/protocol interfaces and system integration requirements.
• Drive quality and delivery timelines for tape-outs and product releases.

Requirements

Must-have technical skills and proven experience; listed are core requirements followed by preferred skills.

• Must-have: Strong proficiency in Verilog / SystemVerilog / VHDL and hands-on RTL design experience.
• Experience with simulation and verification tools (ModelSim, VCS, Xcelium) and building testbenches.
• Experience with synthesis and STA tools (Design Compiler, Genus, PrimeTime) and implementation flows.
• Solid understanding of digital design fundamentals: FSMs, pipelining, clock domain crossing and low-power techniques.
• Familiarity with FPGA/ASIC design flow, bus protocols (AXI, AHB, APB) and use of waveform/debug tools (Verdi, SimVision).
• Proven debugging skills across RTL, gate and silicon and experience supporting post-silicon validation.
• Strong problem-solving, communication and teamwork skills; attention to detail and delivery focus.
• Nice-to-have: UVM-based verification experience, DFT knowledge, scripting (Python/TCL/Perl), hardware-software co-design, and experience with high-speed interfaces or SoC design.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, VLSI Design, or Computer Engineering.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.