Principal DFT Engineer

Job Title

Principal DFT Engineer

Role Summary

Senior DFT engineer on the Connectivity BU DFT team responsible for defining DFT architecture and delivering testability solutions for networking IPs and SoCs.

Lead implementation, verification, and post-silicon bring-up of Scan, ATPG, MBIST, JTAG and related DFT/DFX features while mentoring team members and coordinating with design, physical, STA, validation and ATE teams.

Experience Level

Senior - requires extensive industry experience (see Education Requirements for degree-specific years guidance).

Responsibilities

Primary responsibilities include DFT architecture, implementation, verification, integration, and silicon bring-up.

• Define and drive DFT architecture and test strategy for complex IPs and full chips.
• Lead implementation and integration of Scan, ATPG, JTAG, MBIST and Boundary Scan solutions.
• Develop and deploy test structures, ATPG fault models, test-point insertion, coverage optimization, and scan insertion at block and chip levels.
• Own hierarchical DFT flows from IP level through full-chip integration and tape-out.
• Validate and debug DFT/DFX features; perform RTL and netlist verification and gate-level simulations (zero-delay and SDF-based).
• Generate and validate production test patterns and support test-mode validation and ATE debug.
• Create and maintain test timing constraints (SDC), perform test-mode timing analysis, and support block- and chip-level STA signoff.
• Collaborate with Design, Synthesis, Physical Design, STA, Validation and Silicon Bring-up teams to resolve DFT issues.
• Drive post-silicon bring-up, silicon characterization, and production ramp activities to achieve manufacturing release.

Requirements

Technical must-haves for the role (education details are in the Education Requirements section).

• Hands-on experience across DFT execution stages: scan insertion, MBIST, ATPG, validation, STA, and post-silicon bring-up.
• Proven experience leading DFT activities and mentoring engineers across multiple projects.
• Thorough knowledge of DFT/test architecture and prior involvement defining DFT architecture for multiple designs.
• Strong fundamentals in digital and logic design.
• Experience with industry EDA toolsets (Cadence/Mentor/Synopsys tool chains such as Genus, Modus, NCSim, DC, Tessent, Spyglass, Tmax).
• Experience owning complete DFT responsibility for one or more successful chip tape-outs.
• Experience with production test pattern generation, ATE debug, and silicon validation workflows.
• Scripting skills (Perl, Tcl) for flow automation are a plus.
• Strong ownership, accountability and technical leadership to meet quality and schedule targets.

Education Requirements

Master's degree or PhD in Computer Science, Electrical Engineering or related technical field with 12+ years of experience; alternatively, a Bachelor's degree in Electronics, Electrical Engineering or related field with 14+ years of related professional experience. No specific certifications were listed.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.