Skip to main content
Celero logo

Principal DFT Engineer

Celero
September 21, 2026
Full-time
On-site
Irvine, California, United States
DFT Jobs, Level - Senior

Job Title

Principal DFT Engineer

Role Summary

Implement and drive Design-for-Test (DFT) methodologies for complex ASIC and SoC products to ensure high-quality, high-volume production and manufacturing test readiness. The role partners with RTL, verification, physical design, and manufacturing teams through signoff, silicon bring-up, and yield improvement.

Experience Level

Senior - typically requires 8+ years of ASIC/SoC DFT experience.

Responsibilities

Primary responsibilities include architecture, implementation, validation, and production readiness of on-chip test features and flows.

  • Develop and implement DFT architecture for ASIC and SoC designs.
  • Perform scan insertion, scan chain planning, and scan compression implementation.
  • Generate and validate ATPG patterns and analyze fault coverage results.
  • Implement and verify MBIST and other on-chip test features.
  • Collaborate with RTL, verification, and physical design teams for DFT integration.
  • Support JTAG and boundary-scan implementation and debugging.
  • Drive DFT signoff activities and manufacturing test readiness.
  • Participate in silicon bring-up, failure analysis, and yield improvement efforts.

Requirements

Must-have technical skills and experience.

  • 8+ years of ASIC/SoC DFT experience.
  • Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
  • Hands-on experience with tools such as Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent.
  • Knowledge of Verilog/SystemVerilog and digital design fundamentals.
  • Experience with Linux and scripting (Python, Tcl, Perl, or Shell).
  • Strong debugging and problem-solving abilities.

Nice-to-have

  • Experience with advanced-node semiconductor technologies.
  • Hands-on experience with MBIST, compression architectures, and JTAG.
  • Knowledge of timing closure, physical design impacts, and low-power design techniques.
  • Experience supporting silicon validation and manufacturing production ramps.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.


About the Company

Company: Celero

Celero is a technology company focused on semiconductor design and engineering services, hiring for roles in ASIC/SoC design, test and verification including DFT engineering to support production readiness and silicon bring-up.

Celero logo

Date Posted: 2026-09-16