Principal DFT Engineer

Job Title

Principal DFT Engineer

Role Summary

Lead design-for-test (DFT) efforts for Broadcom ASICs from chip-level specification through implementation, verification, and production release. Work within the ASIC Product Division at the San Jose development center, coordinating with physical design, STA, test engineering, manufacturing, and customers as required.

Experience Level

Senior level — requires extensive industry experience (see Education Requirements for specific years-of-experience guidance).

Responsibilities

Accountable for defining and delivering DFT solutions and test flows to meet product test metrics and release targets.

• Define chip-level DFT specifications based on product and customer test goals.
• Implement DFT: scan, MBIST, TAP, LBIST, IO and SerDes DFT integration, and other IP-level DFT.
• Work with STA and physical design teams to achieve timing closure in DFT modes.
• Generate, verify and debug ATPG/test vectors prior to tape-out.
• Validate and debug test vectors on ATE during silicon bring-up and failure analysis.
• Support silicon diagnostics, yield improvement and customer returns analysis on ATE.
• Interface with customers and cross-functional teams globally during development and debug.
• Develop and automate DFT and test-vector generation flows; innovate solutions for advanced nodes (7nm and beyond).

Requirements

Technical skills and experience required to perform the role. Degree and years-of-experience are listed under Education Requirements.

• Must-have: Strong DFT background (ATPG, scan, BIST, IO/analog DFT); experience with scan insertion and compression tools (e.g., DFT Compiler, Mentor TestKompress).
• Proven experience with ATPG vector generation, simulation and debugging (e.g., TetraMax, Fastscan).
• Verilog coding, testbench generation and simulation experience.
• Memory BIST insertion and verification on embedded memories (SRAM, CAM, eDRAM, ROM).
• Boundary-scan (IEEE 1149.x) verification and test-vector generation knowledge.
• Practical knowledge of Test-STA and timing constraints for test modes.
• Experience with IEE1687/IJTAG, ICL and PDL.
• Proficiency scripting or programming in languages such as TCL, Perl, Ruby, Python, or C++ to automate flows and tools.
• Strong debugging, root-cause analysis and cross-functional collaboration skills.
• Nice-to-have: ATE experience; SerDes, DDR, PCIe, Ethernet, CXL IOBIST verification and silicon debug; Tessent SSN experience.

Education Requirements

Bachelor's degree in Electrical, Electronic or Computer Engineering with 12+ years of relevant industry experience, or Master's degree in Electrical, Electronic or Computer Engineering with 10+ years of relevant industry experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.