Principal DFT Engineer

Job Title

Principal DFT Engineer

Role Summary

The Principal DFT Engineer will lead chip-level Design for Test (DFT) execution, ensuring quality implementation from architecture through to silicon bring-up. This role requires technical leadership and collaboration with various stakeholders to achieve project success.

Experience Level

Senior; typically requires 10+ years of experience in Design for Test engineering.

Responsibilities

Key responsibilities include:

• Lead DFT strategy definition and implementation for chip-level testability.
• Provide expert guidance and solve complex technical challenges in DFT.
• Manage large, technically complex projects while maintaining best practices and quality outputs.
• Mentor junior engineers and foster teamwork environment.
• Contribute to technical thought leadership and customer engagement initiatives.

Requirements

Essential qualifications and skills required:

• A degree, masters, or PhD in a relevant engineering field.
• Typically 10+ years of experience in Design for Test (DFT).
• Expertise in DFT tools such as IJTAG, scan compression, MBIST, among others.
• Strong project management, problem-solving, and leadership skills.
• Ability to define solutions and drive project delivery.

Education Requirements

A degree, masters, or PhD in a relevant subject is required.

About the Company

Company: Aion Silicon

Headquarters: London, United Kingdom

Aion Silicon is a global engineering firm specializing in design solutions for ASIC and SoC development. With design centers in the UK, Spain, India, and Morocco, Aion Silicon focuses on innovative digital IP designs and integrates various designs into customer projects, aiming for high quality and efficiency. They seek experienced professionals passionate about design and technology to join their team in leading projects and advancements in the semiconductor industry.