Principal Design Verification Engineer – High Performance CPU Subsystem

Job Title

Principal Design Verification Engineer – High Performance CPU Subsystem

Role Summary

Principal individual-contributor responsible for defining and executing verification strategy for a high-performance out-of-order CPU subsystem and its coherent interconnect. Works across architecture, RTL, formal, performance, and verification teams to find, debug, and close complex subsystem-level issues and raise verification quality organization-wide.

Experience Level

Senior — Principal-level role. The posting requests 12+ years of relevant experience and deep domain expertise.

Responsibilities

Lead verification planning and execution from block level through subsystem integration and signoff; select and apply methods that best expose risks.

• Define verification strategy and closure criteria for OoO core behaviors (branch prediction, fetch, dispatch, pipeline interactions, load/store ordering, hazards, memory consistency, hardware prefetch).
• Define verification strategy and closure for coherent interconnects: protocol correctness, ordering, backpressure, buffering, arbitration, QoS, and error handling.
• Own verification planning, execution, debug, coverage analysis, and closure across blocks and subsystem integration.
• Develop checkers, scoreboards, assertions, stimulus, and coverage models targeting corner cases and subsystem interactions.
• Apply simulation, formal, and emulation appropriately to improve quality and turnaround on large workloads.
• Drive failure analysis and root-cause debug across architecture, RTL, tests, and infrastructure.
• Partner with architects and designers early to review specs, remove ambiguity, and improve debugability.
• Mentor engineers and influence team methodology; create reusable verification approaches and infrastructure.

Requirements

Must-have technical experience and skills for immediate contribution at the principal level.

• 12+ years of CPU/core or SoC functional verification experience; principal-level depth and leadership.
• Direct experience with out-of-order core verification and strong CPU microarchitecture knowledge.
• Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, and ordering/flow-control verification.
• Deep expertise in areas such as Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
• Strong verification methodology skills: test planning, stimulus generation, failure analysis, coverage analysis, and closure.
• Strong debug skills and ability to translate architectural intent into verification strategy.
• Strong software development, scripting, and automation skills for scalable DV infrastructure.
• 8+ years direct experience on memory management verification (including MMU/IO-MMU, hypervisor/virtualization contexts) — listed separately by the employer.
• Proven ability to drive cross-team technical leadership and mentor other engineers.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field (specified by the employer).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.